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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-08-14 14:23:12 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-08-14 15:26:11 +0200 |
commit | faacc7ad897437a8169af9dbbab6818f88c7b1a9 (patch) | |
tree | 8ef1b7953a3cc61aac19172ef680864f0b29b53b /tests | |
parent | 539d4ee90767a839b1c3689dedb6c161b652410f (diff) | |
download | yosys-faacc7ad897437a8169af9dbbab6818f88c7b1a9.tar.gz yosys-faacc7ad897437a8169af9dbbab6818f88c7b1a9.tar.bz2 yosys-faacc7ad897437a8169af9dbbab6818f88c7b1a9.zip |
proc_prune: Make assign removal and promotion per-bit, remember promoted bits.
Fixes #2962.
Diffstat (limited to 'tests')
-rw-r--r-- | tests/proc/bug2962.ys | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/proc/bug2962.ys b/tests/proc/bug2962.ys new file mode 100644 index 000000000..99da8db5d --- /dev/null +++ b/tests/proc/bug2962.ys @@ -0,0 +1,22 @@ +read_ilang << EOT +module \top + wire width 4 input 1 \a + wire width 2 input 2 \b + wire input 3 \clk + wire width 4 output 4 \q + wire input 5 \en + wire width 4 \nq + process \p + assign \nq \a + assign \nq [1:0] \b + switch \en + case 1'1 + assign \nq [3] 1'0 + end + sync posedge \clk + update \q \nq + end +end +EOT +proc +check -assert |