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Age
Files
Lines
*
sv: fix up end label checking
Zachary Snow
2021-06-16
6
-0
/
+80
*
Add regression test for #2824.
Marcelina Kościelnicka
2021-06-11
1
-0
/
+7
*
Merge pull request #2817 from YosysHQ/claire/fixemails
Claire Xen
2021-06-09
7
-79
/
+79
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*
More deadname stuff
Claire Xenia Wolf
2021-06-09
2
-4
/
+4
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*
More deadname stuff
Claire Xenia Wolf
2021-06-09
1
-1
/
+1
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*
Use HTTPS for website links, gatecat email
Claire Xenia Wolf
2021-06-09
1
-1
/
+1
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*
Fix files with CRLF line endings
Claire Xenia Wolf
2021-06-09
3
-73
/
+73
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*
Fixing old e-mail addresses and deadnames
Claire Xenia Wolf
2021-06-08
1
-1
/
+1
*
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verilog: check for module scope identifiers during width detection
Zachary Snow
2021-06-08
1
-0
/
+11
*
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mem2reg: tolerate out of bounds constant accesses
Zachary Snow
2021-06-08
3
-0
/
+52
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/
*
sv: support tasks and functions within packages
Zachary Snow
2021-06-01
2
-0
/
+34
*
memory_map: Improve start_offset handling.
Marcelina Kościelnicka
2021-05-31
1
-0
/
+100
*
memory_bram: Reuse extract_rdff helper for make_outreg.
Marcelina Kościelnicka
2021-05-25
4
-17
/
+14
*
verilog: fix case expression sign and width handling
Zachary Snow
2021-05-25
2
-0
/
+108
*
sv: support remaining assignment operators
Zachary Snow
2021-05-25
1
-0
/
+23
*
opt_mem_feedback: Respect write port priority.
Marcelina Kościelnicka
2021-05-25
1
-0
/
+47
*
opt_mem_feedback: Rewrite feedback path finding logic.
Marcelina Kościelnicka
2021-05-24
2
-0
/
+243
*
Add new helper class for merging FFs into cells, use for memory_dff.
Marcelina Kościelnicka
2021-05-23
1
-0
/
+17
*
opt_mem: Remove write ports with const-0 EN.
Marcelina Kościelnicka
2021-05-23
1
-0
/
+34
*
tests/blif: Add missing gitignore
Marcelina Kościelnicka
2021-05-20
1
-0
/
+1
*
intel_alm: Fix illegal carry chains
gatecat
2021-05-15
2
-4
/
+4
*
intel_alm: Add global buffer insertion
gatecat
2021-05-15
13
-41
/
+41
*
intel_alm: Add IO buffer insertion
gatecat
2021-05-15
13
-39
/
+39
*
sv: check validity of package end label
Zachary Snow
2021-05-10
1
-0
/
+15
*
blif: Use library cells' start_offset and upto for wideports.
Marcelina Kościelnicka
2021-05-08
2
-0
/
+26
*
opt_dff: Fix NOT gates wired in reverse.
Marcelina Kościelnicka
2021-05-04
1
-8
/
+13
*
Add default assignments to SB_LUT4
Claire Xenia Wolf
2021-04-20
1
-1
/
+1
*
quicklogic: ABC9 synthesis
Lofty
2021-04-17
6
-17
/
+17
*
preproc: test coverage for #2712
Zachary Snow
2021-03-30
3
-0
/
+18
*
abc9: uniquify blackboxes like whiteboxes (#2695)
Eddie Hung
2021-03-29
1
-1
/
+56
*
abc9: fix SCC issues (#2694)
Eddie Hung
2021-03-29
3
-12
/
+27
*
quicklogic: Add .gitignore file for test outputs.
Marcelina Kościelnicka
2021-03-23
1
-0
/
+4
*
verilog: check entire user type stack for type definition
Xiretza
2021-03-21
1
-0
/
+10
*
sv: allow typenames as function return types
Zachary Snow
2021-03-19
2
-0
/
+40
*
quicklogic: PolarPro 3 support
Lofty
2021-03-18
10
-0
/
+262
*
ast: Use better parameter serialization for paramod names.
Marcelina Kościelnicka
2021-03-18
1
-3
/
+3
*
Blackbox all whiteboxes after synthesis
gatecat
2021-03-17
1
-9
/
+9
*
sv: carry over global typedefs from previous files
Zachary Snow
2021-03-17
2
-0
/
+60
*
verilog: fix buf/not primitives with multiple outputs
Xiretza
2021-03-17
1
-0
/
+15
*
blackbox: Include whiteboxed modules
gatecat
2021-03-17
1
-0
/
+14
*
verilog: support module scope identifiers in parametric modules
Zachary Snow
2021-03-16
1
-0
/
+29
*
proc_arst: Add special-casing of clock signal in conditionals.
Marcelina Kościelnicka
2021-03-15
1
-0
/
+31
*
opt_clean: Remove init attribute bits together with removed DFFs.
Marcelina Kościelnicka
2021-03-15
1
-11
/
+20
*
rtlil: Disallow 0-width chunks in SigSpec.
Marcelina Kościelnicka
2021-03-15
1
-0
/
+14
*
sv: allow globals in one file to depend on globals in another
Zachary Snow
2021-03-12
1
-0
/
+20
*
verilog: disallow overriding global parameters
Zachary Snow
2021-03-11
1
-0
/
+16
*
memory_dff: Remove now-useless write port handling.
Marcelina Kościelnicka
2021-03-08
2
-2
/
+1
*
proc_dff: Fix emitted FF when a register is not assigned in async reset
Marcelina Kościelnicka
2021-03-08
1
-0
/
+23
*
tests/bram: Do not generate write address collisions.
Marcelina Kościelnicka
2021-03-08
1
-5
/
+23
*
Merge pull request #2626 from zachjs/param-no-default
whitequark
2021-03-07
10
-0
/
+177
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