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Author
Age
Files
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Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
Eddie Hung
2019-06-10
2
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+53
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Add test
Eddie Hung
2019-06-10
2
-0
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+53
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-06-10
1
-1
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+6
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Add some more comments
Eddie Hung
2019-06-10
1
-1
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+6
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-06-07
28
-33
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+138
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Test *.aag too, by using *.aig as reference
Eddie Hung
2019-06-07
1
-0
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+19
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Use ABC to convert from AIGER to Verilog
Eddie Hung
2019-06-07
1
-2
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+3
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Use ABC to convert AIGER to Verilog, then sat against Yosys
Eddie Hung
2019-06-07
1
-21
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+15
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Add symbols to AIGER test inputs for ABC
Eddie Hung
2019-06-07
22
-8
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+40
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Merge pull request #1077 from YosysHQ/clifford/pr983
Clifford Wolf
2019-06-07
2
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+31
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Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...
Clifford Wolf
2019-06-07
2
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+31
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Initial implementation of elaboration system tasks
Udi Finkelstein
2019-05-03
2
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+31
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Rename implicit_ports.sv test to implicit_ports.v
Clifford Wolf
2019-06-07
1
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+0
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Cleanup tux3-implicit_named_connection
Clifford Wolf
2019-06-07
2
-12
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+1
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Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...
Clifford Wolf
2019-06-07
4
-3
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+42
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SystemVerilog support for implicit named port connections
tux3
2019-06-06
4
-3
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+42
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Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
Eddie Hung
2019-06-06
2
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+41
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Fix and test for balanced case
Eddie Hung
2019-06-06
2
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+41
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Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
Eddie Hung
2019-06-06
15
-0
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+512
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Fix warnings
Eddie Hung
2019-06-06
2
-3
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+3
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Support cascading $pmux.A with $mux.A and $mux.B
Eddie Hung
2019-06-06
2
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+40
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Add non exclusive test
Eddie Hung
2019-06-06
2
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+56
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One more and tidy up
Eddie Hung
2019-06-06
2
-6
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+28
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Add a few more special case tests
Eddie Hung
2019-06-06
2
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+51
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Add tests, fix for !=
Eddie Hung
2019-06-06
2
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+78
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ...
Maciej Kurc
2019-06-04
4
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+46
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Added tests for attributes
Maciej Kurc
2019-06-03
9
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+219
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-06-03
1
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+4
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Merge pull request #1049 from YosysHQ/clifford/fix1047
Clifford Wolf
2019-05-28
1
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+4
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Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
Clifford Wolf
2019-05-28
1
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+4
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Rename to #23
Eddie Hung
2019-05-29
1
-3
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+3
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Add abc_test024
Eddie Hung
2019-05-29
1
-6
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+19
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Add abc9_test022
Eddie Hung
2019-05-28
1
-0
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+22
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From master
Eddie Hung
2019-05-28
1
-1
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+1
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-05-28
3
-27
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+84
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Add actual wandwor test that is part of "make test"
Clifford Wolf
2019-05-28
2
-33
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+36
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Merge branch 'master' into wandwor
Stefan Biereigel
2019-05-27
2
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+76
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Fix init
Eddie Hung
2019-05-24
1
-27
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+27
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Fix typos
Eddie Hung
2019-05-24
1
-6
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+6
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Add more tests
Eddie Hung
2019-05-24
2
-20
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+41
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Call proc
Eddie Hung
2019-05-24
1
-1
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+1
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Fix duplicate driver
Eddie Hung
2019-05-24
1
-15
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+15
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reformat wand/wor test
Stefan Biereigel
2019-05-27
1
-22
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+21
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remove port direction workaround from test case
Stefan Biereigel
2019-05-27
1
-2
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+1
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add simple test case for wand/wor
Stefan Biereigel
2019-05-23
1
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+35
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Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux
Eddie Hung
2019-05-23
2
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+55
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Add opt_rmdff tests
Eddie Hung
2019-05-23
2
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+55
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-05-21
10
-5
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+225
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Added tests for Verilog frontent for attributes on parameters and localparams
Maciej Kurc
2019-05-16
2
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+22
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Add test case from #997
Clifford Wolf
2019-05-07
1
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+12
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