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* Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7muxEddie Hung2019-06-102-0/+53
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| * Add testEddie Hung2019-06-102-0/+53
* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-101-1/+6
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| * Add some more commentsEddie Hung2019-06-101-1/+6
* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-0728-33/+138
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| * Test *.aag too, by using *.aig as referenceEddie Hung2019-06-071-0/+19
| * Use ABC to convert from AIGER to VerilogEddie Hung2019-06-071-2/+3
| * Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
| * Add symbols to AIGER test inputs for ABCEddie Hung2019-06-0722-8/+40
| * Merge pull request #1077 from YosysHQ/clifford/pr983Clifford Wolf2019-06-072-0/+31
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| | * Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...Clifford Wolf2019-06-072-0/+31
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| | | * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-032-0/+31
| * | | Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
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| * | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-072-12/+1
| * | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...Clifford Wolf2019-06-074-3/+42
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| | * | SystemVerilog support for implicit named port connectionstux32019-06-064-3/+42
* | | | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7muxEddie Hung2019-06-062-0/+41
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| * | | | Fix and test for balanced caseEddie Hung2019-06-062-0/+41
* | | | | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7muxEddie Hung2019-06-0615-0/+512
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| * | | | Fix warningsEddie Hung2019-06-062-3/+3
| * | | | Support cascading $pmux.A with $mux.A and $mux.BEddie Hung2019-06-062-0/+40
| * | | | Add non exclusive testEddie Hung2019-06-062-0/+56
| * | | | One more and tidy upEddie Hung2019-06-062-6/+28
| * | | | Add a few more special case testsEddie Hung2019-06-062-0/+51
| * | | | Add tests, fix for !=Eddie Hung2019-06-062-0/+78
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| * | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ...Maciej Kurc2019-06-044-0/+46
| * | | Added tests for attributesMaciej Kurc2019-06-039-0/+219
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* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-031-0/+4
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| * | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-0/+4
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| | * | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-0/+4
* | | | Rename to #23Eddie Hung2019-05-291-3/+3
* | | | Add abc_test024Eddie Hung2019-05-291-6/+19
* | | | Add abc9_test022Eddie Hung2019-05-281-0/+22
* | | | From masterEddie Hung2019-05-281-1/+1
* | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-283-27/+84
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| * | | Add actual wandwor test that is part of "make test"Clifford Wolf2019-05-282-33/+36
| * | | Merge branch 'master' into wandworStefan Biereigel2019-05-272-0/+76
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| | * | Fix initEddie Hung2019-05-241-27/+27
| | * | Fix typosEddie Hung2019-05-241-6/+6
| | * | Add more testsEddie Hung2019-05-242-20/+41
| | * | Call procEddie Hung2019-05-241-1/+1
| | * | Fix duplicate driverEddie Hung2019-05-241-15/+15
| * | | reformat wand/wor testStefan Biereigel2019-05-271-22/+21
| * | | remove port direction workaround from test caseStefan Biereigel2019-05-271-2/+1
| * | | add simple test case for wand/worStefan Biereigel2019-05-231-0/+35
* | | | Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7muxEddie Hung2019-05-232-0/+55
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| * | | Add opt_rmdff testsEddie Hung2019-05-232-0/+55
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* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-2110-5/+225
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| * | Added tests for Verilog frontent for attributes on parameters and localparamsMaciej Kurc2019-05-162-0/+22
| * | Add test case from #997Clifford Wolf2019-05-071-0/+12
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