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* sv: fix two struct access bugsZachary Snow2021-07-152-0/+92
* Add a test for interfaces on modules loaded on-demandRupert Swarbrick2021-07-145-2/+48
* sv: fix up end label checkingZachary Snow2021-06-166-0/+80
* Add regression test for #2824.Marcelina Kościelnicka2021-06-111-0/+7
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-097-79/+79
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| * More deadname stuffClaire Xenia Wolf2021-06-092-4/+4
| * More deadname stuffClaire Xenia Wolf2021-06-091-1/+1
| * Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-091-1/+1
| * Fix files with CRLF line endingsClaire Xenia Wolf2021-06-093-73/+73
| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-081-0/+11
* | mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-083-0/+52
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* sv: support tasks and functions within packagesZachary Snow2021-06-012-0/+34
* memory_map: Improve start_offset handling.Marcelina Kościelnicka2021-05-311-0/+100
* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-254-17/+14
* verilog: fix case expression sign and width handlingZachary Snow2021-05-252-0/+108
* sv: support remaining assignment operatorsZachary Snow2021-05-251-0/+23
* opt_mem_feedback: Respect write port priority.Marcelina Kościelnicka2021-05-251-0/+47
* opt_mem_feedback: Rewrite feedback path finding logic.Marcelina Kościelnicka2021-05-242-0/+243
* Add new helper class for merging FFs into cells, use for memory_dff.Marcelina Kościelnicka2021-05-231-0/+17
* opt_mem: Remove write ports with const-0 EN.Marcelina Kościelnicka2021-05-231-0/+34
* tests/blif: Add missing gitignoreMarcelina Kościelnicka2021-05-201-0/+1
* intel_alm: Fix illegal carry chainsgatecat2021-05-152-4/+4
* intel_alm: Add global buffer insertiongatecat2021-05-1513-41/+41
* intel_alm: Add IO buffer insertiongatecat2021-05-1513-39/+39
* sv: check validity of package end labelZachary Snow2021-05-101-0/+15
* blif: Use library cells' start_offset and upto for wideports.Marcelina Kościelnicka2021-05-082-0/+26
* opt_dff: Fix NOT gates wired in reverse.Marcelina Kościelnicka2021-05-041-8/+13
* Add default assignments to SB_LUT4Claire Xenia Wolf2021-04-201-1/+1
* quicklogic: ABC9 synthesisLofty2021-04-176-17/+17
* preproc: test coverage for #2712Zachary Snow2021-03-303-0/+18
* abc9: uniquify blackboxes like whiteboxes (#2695)Eddie Hung2021-03-291-1/+56
* abc9: fix SCC issues (#2694)Eddie Hung2021-03-293-12/+27
* quicklogic: Add .gitignore file for test outputs.Marcelina Kościelnicka2021-03-231-0/+4
* verilog: check entire user type stack for type definitionXiretza2021-03-211-0/+10
* sv: allow typenames as function return typesZachary Snow2021-03-192-0/+40
* quicklogic: PolarPro 3 supportLofty2021-03-1810-0/+262
* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-3/+3
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-9/+9
* sv: carry over global typedefs from previous filesZachary Snow2021-03-172-0/+60
* verilog: fix buf/not primitives with multiple outputsXiretza2021-03-171-0/+15
* blackbox: Include whiteboxed modulesgatecat2021-03-171-0/+14
* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-161-0/+29
* proc_arst: Add special-casing of clock signal in conditionals.Marcelina Kościelnicka2021-03-151-0/+31
* opt_clean: Remove init attribute bits together with removed DFFs.Marcelina Kościelnicka2021-03-151-11/+20
* rtlil: Disallow 0-width chunks in SigSpec.Marcelina Kościelnicka2021-03-151-0/+14
* sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-121-0/+20
* verilog: disallow overriding global parametersZachary Snow2021-03-111-0/+16
* memory_dff: Remove now-useless write port handling.Marcelina Kościelnicka2021-03-082-2/+1
* proc_dff: Fix emitted FF when a register is not assigned in async resetMarcelina Kościelnicka2021-03-081-0/+23
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