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* Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-1410-0/+125
|\ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * sv: Improve testsDavid Shah2019-10-038-7/+30
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Add test scripts for typedefsDavid Shah2019-10-034-0/+30
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Add support for memories of a typedefDavid Shah2019-10-031-0/+10
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Add support for memory typedefsDavid Shah2019-10-031-0/+10
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Fix typedefs in packagesDavid Shah2019-10-031-0/+11
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Fix typedef parametersDavid Shah2019-10-032-3/+22
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-0/+22
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Revert "Add test that is expecting to fail"Eddie Hung2019-10-081-20/+0
| | | | | | | | This reverts commit c28d4b804720c2cf0086e921748219150e9631b5.
* | Merge pull request #1432 from YosysHQ/eddie/fix1427Eddie Hung2019-10-082-2/+60
|\ \ | | | | | | Refactor peepopt_dffmux and be sensitive to \init when trimming
| * | Use `sat -tempinduct` and comments for why equiv_opt not sufficientEddie Hung2019-10-031-1/+8
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| * | Fix broken CI, check reset even for constants, trim rstmuxEddie Hung2019-10-021-2/+2
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| * | Fix testEddie Hung2019-10-021-2/+12
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| * | Merge branch 'eddie/fix_sat_init' into eddie/fix1427Eddie Hung2019-10-021-0/+20
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| | * | Add test that is expecting to failEddie Hung2019-10-021-0/+20
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| * | | Update testEddie Hung2019-10-021-13/+3
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| * | | Add testEddie Hung2019-10-021-0/+31
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* | | Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2syncEddie Hung2019-10-082-9/+4
|\ \ \ | | | | | | | | async2sync to be called by equiv_opt only when -async2sync given
| * | | Disable equiv check for ice40 latchesEddie Hung2019-10-031-6/+3
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| * | | Use equiv_opt -async2sync for xilinxEddie Hung2019-10-031-3/+1
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* | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolfEddie Hung2019-10-051-0/+22
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* | | Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-031-0/+10
|\ \ \ | |_|/ |/| | Add -select option to aigmap
| * | Add quick testEddie Hung2019-09-301-0/+10
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* | Extend test with renaming cells with prefix tooEddie Hung2019-10-021-0/+2
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* | Add testEddie Hung2019-09-301-0/+16
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* Merge pull request #1406 from whitequark/connect_rpcwhitequark2019-09-306-0/+152
|\ | | | | rpc: new frontend
| * rpc: new frontend.whitequark2019-09-306-0/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design.
* | Add latch test modified from #1363Eddie Hung2019-09-302-0/+73
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* | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2910-11/+325
|\ \ | | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5)
| * \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-231-0/+62
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| * | | Add more complicated macc testcaseEddie Hung2019-09-192-5/+39
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| * | | Add mac.sh and macc_tb.v for testingEddie Hung2019-09-192-0/+99
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| * | | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dspEddie Hung2019-09-191-0/+41
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| * | | | Format macc.vEddie Hung2019-09-191-8/+8
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| * | | | Remove statEddie Hung2019-09-181-1/+0
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| * | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-181-2/+26
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| * | | | | Add .gitignoreEddie Hung2019-09-181-0/+1
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| * | | | | Refine macc testcaseEddie Hung2019-09-182-9/+17
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| * | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-123-1/+63
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| * | | | | | Add AREG=2 BREG=2 testEddie Hung2019-09-111-2/+6
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| * | | | | | Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dspEddie Hung2019-09-111-0/+71
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| * | | | | | | Update test with a/b resetEddie Hung2019-09-111-2/+4
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| * | | | | | | Extend test for RSTP and RSTMEddie Hung2019-09-112-3/+50
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dspEddie Hung2019-09-111-1/+18
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| * \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dspEddie Hung2019-09-111-6/+6
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| * \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-112-7/+105
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| * | | | | | | | | | Add SIMD testEddie Hung2019-09-091-0/+25
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| * | | | | | | | | | Update macc testEddie Hung2019-09-062-42/+42
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| * | | | | | | | | | Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dspEddie Hung2019-09-052-21/+63
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| * \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-051-1/+3
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