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* Proper example codeMiodrag Milanovic2022-03-142-1/+3
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* intel_alm: M10K write-enable is negative-trueLofty2022-03-091-1/+2
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* Merge pull request #3207 from nakengelhardt/json_escape_quotesMiodrag Milanović2022-03-042-0/+15
|\ | | | | fix handling of escaped chars in json backend and frontend (mostly)
| * fix handling of escaped chars in json backend and frontendN. Engelhardt2022-02-182-0/+15
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* | test dlatchsr and adlatchMiodrag Milanovic2022-02-164-4/+94
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* | Added test casesMiodrag Milanovic2022-02-1638-0/+896
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* verilog: support for time scale delay valuesZachary Snow2022-02-141-0/+25
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* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-144-5/+51
| | | | | | * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: fix dynamic dynamic range asgn elabZachary Snow2022-02-112-0/+108
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* verilog: fix const func eval with upto variablesZachary Snow2022-02-112-0/+84
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* gowin: Fix LUT RAM inference, add more models.Marcelina Kościelnicka2022-02-091-3/+2
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* Merge pull request #3185 from YosysHQ/micko/co_simMiodrag Milanović2022-02-077-0/+953
|\ | | | | Add co-simulation in sim pass
| * bug fix and cleanupsMiodrag Milanovic2022-02-041-2/+2
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| * Add test cases for co-simulationMiodrag Milanovic2022-02-027-0/+953
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* | opt_reduce: Add $bmux and $demux optimization patterns.Marcelina Kościelnicka2022-01-302-0/+208
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* Merge pull request #3120 from Icenowy/anlogic-bramMiodrag Milanović2022-01-192-1/+14
|\ | | | | anlogic: support BRAM mapping
| * anlogic: support BRAM mappingIcenowy Zheng2021-12-172-1/+14
| | | | | | | | | | | | | | | | | | | | | | Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-078-0/+135
| | | | | | | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
* | sv: fix size cast internal expression extensionZachary Snow2022-01-072-0/+145
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* | logger: fix unmatched expected warnings and errorsZachary Snow2022-01-041-0/+42
| | | | | | | | | | | | | | | | - Prevent unmatched expected error patterns from self-matching - Prevent infinite recursion on unmatched expected warnings - Always print the error message for unmatched error patterns - Add test coverage for all unmatched message types - Add test coverage for excess matched logs and warnings
* | fix iverilog compatibility for new case expr testsZachary Snow2022-01-032-2/+2
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* | fixup verilog doubleslash testZachary Snow2022-01-032-0/+3
| | | | | | | | | | - add generated doubleslash.v to .gitignore - ensure backend verilog can be read again
* | sv: fix size cast clipping expression widthZachary Snow2022-01-031-0/+7
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* | memory_share: Fix SAT-based sharing for wide ports.Marcelina Kościelnicka2021-12-201-0/+34
| | | | | | | | Fixes #3117.
* | fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-172-0/+43
|/ | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
* preprocessor: do not destroy double slash escaped identifiersThomas Sailer2021-12-151-0/+19
| | | | | | | | | | | The preprocessor currently destroys double slash containing escaped identifiers (for example \a//b ). This is due to next_token trying to convert single line comments (//) into /* */ comments. This then leads to an unintuitive error message like this: ERROR: syntax error, unexpected '*' This patch fixes the error by recognizing escaped identifiers and returning them as single token. It also adds a testcase.
* Fix the tests we just brokeClaire Xenia Wolf2021-12-106-10/+10
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Add gitignore for gatemateMiodrag Milanovic2021-12-031-0/+4
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* sta: very crude static timing analysis passLofty2021-11-251-0/+81
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-161-0/+51
| | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* synth_gatemate: Update passPatrick Urban2021-11-131-4/+8
| | | | | | * remove `write_edif` and `write_blif` options * remove redundant `abc` call before muxcover * update style
* synth_gatemate: Apply new test practice with assert-maxPatrick Urban2021-11-137-12/+12
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* synth_gatemate: Fix fsm testPatrick Urban2021-11-131-2/+2
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* Allow initial blocks to be disabled during testsPatrick Urban2021-11-136-4/+20
| | | | Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail.
* synth_gatemate: Initial implementationPatrick Urban2021-11-1314-0/+337
| | | | Signed-off-by: Patrick Urban <patrick.urban@web.de>
* iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-092-3/+3
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* dfflegalize: Add tests for aldff lowering.Marcelina Kościelnicka2021-10-272-0/+240
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* dfflegalize: Add tests targetting aldff.Marcelina Kościelnicka2021-10-277-7/+320
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* dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-279-73/+46
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* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-254-0/+79
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* extract_reduce: Refactor and fix input signal construction.Marcelina Kościelnicka2021-10-211-0/+12
| | | | Fixes #3047.
* Fixes in vcdcd.pl for newer Perl versionsClaire Xenia Wolf2021-10-191-3/+3
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fix a regression from #3035.Marcelina Kościelnicka2021-10-081-0/+21
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* FfData: some refactoring.Marcelina Kościelnicka2021-10-072-5/+7
| | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
* Merge pull request #3014 from YosysHQ/claire/fix-vgtestClaire Xen2021-09-2440-79/+79
|\ | | | | Fix "make vgtest"
| * Fix "make vgtest" so it runs to the end (but now it fails ;)Claire Xenia Wolf2021-09-2340-79/+79
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | sv: support wand and wor of data typesZachary Snow2021-09-212-0/+39
| | | | | | | | | | | | This enables the usage of declarations of wand or wor with a base type of logic, integer, or a typename. Note that declarations of nets with 2-state base types is still permitted, in violation of the spec.
* | verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-212-0/+100
|/ | | | | | | | - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
* abc9: make re-entrant (#2993)Eddie Hung2021-09-091-0/+20
| | | | | | | | | * Add testcase * Cleanup some state at end of abc9 * Re-assign abc9_box_id from scratch * Suppress delete unless prep_bypass did something
* abc9: holes module to instantiate cells with NEW_ID (#2992)Eddie Hung2021-09-091-0/+14
| | | | | * Add testcase * holes module to instantiate cells with NEW_ID
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