| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix FIRRTL to Verilog process instance subfield assignment. | Jim Lawson | 2019-02-25 | 3 | -3/+1 |
| | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`) | ||||
| * | Merge pull request #812 from ucb-bar/arrayhierarchyfixes | Clifford Wolf | 2019-02-24 | 2 | -1/+68 |
| |\ | | | | | Define basic_cell_type() function and use it to derive the cell type … | ||||
| | * | Address requested changes - don't require non-$ name. | Jim Lawson | 2019-02-22 | 2 | -4/+7 |
| | | | | | | | | | | | | | Suppress warning if name does begin with a `$`. Fix hierachy tests so they have something to grep. Announce hierarchy test types. | ||||
| | * | Fix normal (non-array) hierarchy -auto-top. | Jim Lawson | 2019-02-19 | 2 | -1/+65 |
| | | | | | | | | | Add simple test. | ||||
| * | | Merge pull request #824 from litghost/fix_reduce_on_ff | Clifford Wolf | 2019-02-24 | 2 | -0/+24 |
| |\ \ | | | | | | | Fix WREDUCE on FF not fixing ARST_VALUE parameter. | ||||
| | * | | Fix WREDUCE on FF not fixing ARST_VALUE parameter. | Keith Rothman | 2019-02-22 | 2 | -0/+24 |
| | | | | | | | | | | | | | | | | | | | Adds test case that fails without code change. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | | | Fix handling of defparam for when default_nettype is none | Clifford Wolf | 2019-02-24 | 1 | -0/+2 |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Revert "Add -B option to autotest.sh to append to backend_opts" | Eddie Hung | 2019-02-21 | 1 | -4/+2 |
| | | | | | | | | | This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b. | ||||
| * | | Remove simple_defparam tests | Eddie Hung | 2019-02-20 | 1 | -21/+0 |
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| * | | Merge https://github.com/YosysHQ/yosys into dff_init | Eddie Hung | 2019-02-17 | 5 | -8/+93 |
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| | * | | Append (instead of over-writing) EXTRA_FLAGS | Jim Lawson | 2019-02-15 | 1 | -1/+1 |
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| | * | | Update cells supported for verilog to FIRRTL conversion. | Jim Lawson | 2019-02-15 | 4 | -7/+92 |
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail. | ||||
| * | | Add tests for simple cases using defparam | Eddie Hung | 2019-02-06 | 1 | -0/+21 |
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| * | | Add -B option to autotest.sh to append to backend_opts | Eddie Hung | 2019-02-06 | 1 | -2/+4 |
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| * | | Extend testcase | Eddie Hung | 2019-02-06 | 1 | -2/+34 |
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| * | | Add testcase | Eddie Hung | 2019-02-06 | 1 | -0/+10 |
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| * | Remove asicworld tests for (unsupported) switch-level modelling | Clifford Wolf | 2019-01-27 | 4 | -69/+0 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge pull request #770 from whitequark/opt_expr_cmp | Clifford Wolf | 2019-01-02 | 2 | -0/+44 |
| |\ | | | | | opt_expr: refactor and improve simplification of comparisons | ||||
| | * | opt_expr: improve simplification of comparisons with large constants. | whitequark | 2019-01-02 | 1 | -0/+18 |
| | | | | | | | | | | | | | | | | | | | | | | | | | The idea behind this simplification is that a N-bit signal X being compared with an M-bit constant where M>N and the constant has Nth or higher bit set, it either always succeeds or always fails. However, the existing implementation only worked with one-hot signals for some reason. It also printed incorrect messages. This commit adjusts the simplification to have as much power as possible, and fixes other bugs. | ||||
| | * | opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI. | whitequark | 2019-01-02 | 1 | -0/+5 |
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| | * | opt_expr: refactor simplification of signed X>=0 and X<0. NFCI. | whitequark | 2019-01-02 | 1 | -8/+14 |
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| | * | opt_expr: simplify any unsigned comparisons with all-0 and all-1. | whitequark | 2019-01-02 | 2 | -0/+15 |
| | | | | | | | | | | | | | Before this commit, only unsigned comparisons with all-0 would be simplified. This commit also makes the code handling such comparisons to be more rigorous and not abort on unexpected input. | ||||
| * | | cmp2lut: new techmap pass. | whitequark | 2019-01-02 | 3 | -2/+33 |
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| * | opt_lut: eliminate LUTs evaluating to constants or inputs. | whitequark | 2018-12-31 | 3 | -0/+23 |
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| * | Squelch a little more trailing whitespace | Larry Doolittle | 2018-12-29 | 1 | -1/+1 |
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| * | Merge pull request #724 from whitequark/equiv_opt | Clifford Wolf | 2018-12-16 | 3 | -26/+3 |
| |\ | | | | | equiv_opt: new command, for verifying optimization passes | ||||
| | * | equiv_opt: pass -D EQUIV when techmapping. | whitequark | 2018-12-07 | 2 | -4/+1 |
| | | | | | | | | | | | This allows avoiding techmap crashes e.g. because of large memories in white-box cell models. | ||||
| | * | equiv_opt: new command, for verifying optimization passes. | whitequark | 2018-12-07 | 2 | -23/+3 |
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| * | | opt_lut: leave intact LUTs with cascade feeding module outputs. | whitequark | 2018-12-07 | 2 | -0/+20 |
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| * | | Add missing .gitignore | Clifford Wolf | 2018-12-06 | 1 | -0/+8 |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. | whitequark | 2018-12-05 | 8 | -0/+45 |
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| * | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. | whitequark | 2018-12-05 | 1 | -1/+1 |
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| * | opt_lut: new pass, to combine LUTs for tighter packing. | whitequark | 2018-12-05 | 5 | -0/+43 |
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| * | Merge pull request #679 from udif/pr_syntax_error | Clifford Wolf | 2018-10-25 | 13 | -0/+64 |
| |\ | | | | | More meaningful SystemVerilog/Verilog parser error messages | ||||
| | * | Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵ | Udi Finkelstein | 2018-10-25 | 13 | -0/+64 |
| | | | | | | | | | | | | | | | parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages. | ||||
| * | | Support for SystemVerilog interfaces as a port in the top level module + ↵ | Ruben Undheim | 2018-10-20 | 7 | -2/+420 |
| |/ | | | | test case | ||||
| * | Basic test for checking correct synthesis of SystemVerilog interfaces | Ruben Undheim | 2018-10-18 | 5 | -9/+246 |
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| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -3/+17 |
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| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -0/+76 |
| | | | | | This time doing the changes mostly in AST before RTLIL generation | ||||
| * | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 2 | -0/+75 |
| |\ | | | | | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test) | ||||
| | * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -4/+38 |
| | | | | | | | | | No longer false warnings for memories and assertions | ||||
| | * | reg_wire_error test needs the -sv flag so it is run via a script so it had ↵ | Udi Finkelstein | 2018-06-05 | 2 | -0/+1 |
| | | | | | | | | | to be moved out of the tests/simple dir that only runs Verilog files | ||||
| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 1 | -0/+40 |
| | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) | ||||
| * | | Fixed typo (sikp -> skip) | Udi Finkelstein | 2018-06-05 | 1 | -1/+1 |
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| * | | autotest.sh: Change from /bin/bash to /usr/bin/env bash | Johnny Sorocil | 2018-05-06 | 1 | -1/+1 |
| | | | | | | | | | | | This enables running tests on Unix systems which are not shipped with bash installed in /bin/bash (eg *BSDs and Solaris). | ||||
| * | | Fix tests/simple/specify.v | Clifford Wolf | 2018-03-27 | 1 | -2/+2 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | First draft of Verilog parser support for specify blocks and parameters. | Udi Finkelstein | 2018-03-27 | 1 | -0/+31 |
| |/ | | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST | ||||
| * | Major redesign of Verific SVA importer | Clifford Wolf | 2018-02-27 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add support for SVA throughout via Verific | Clifford Wolf | 2018-02-21 | 1 | -1/+1 |
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| * | Add support for SVA sequence concatenation ranges via verific | Clifford Wolf | 2018-02-18 | 2 | -0/+20 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
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index : iCE40/yosys | |
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