diff options
| author | Clifford Wolf <clifford@clifford.at> | 2018-02-27 20:33:15 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-27 20:33:15 +0100 |
| commit | 25e33d7ab8ebeb96d6a7fb842e33f35770367587 (patch) | |
| tree | ebe4be4efe31ed5092ad86969706b04f2df2095d /tests | |
| parent | 6f26695d9b596fe3b221334a93c5d94678582aea (diff) | |
| download | yosys-25e33d7ab8ebeb96d6a7fb842e33f35770367587.tar.gz yosys-25e33d7ab8ebeb96d6a7fb842e33f35770367587.tar.bz2 yosys-25e33d7ab8ebeb96d6a7fb842e33f35770367587.zip | |
Major redesign of Verific SVA importer
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/sva/sva_range.sv | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/sva/sva_range.sv b/tests/sva/sva_range.sv index 38199bff1..d1569fc83 100644 --- a/tests/sva/sva_range.sv +++ b/tests/sva/sva_range.sv @@ -5,7 +5,7 @@ module top ( default clocking @(posedge clk); endclocking assert property ( - a ##[*] b |=> c until ##[*] d + a ##[*] b |=> c until d ); `ifndef FAIL |