| Commit message (Collapse) | Author | Age | Files | Lines |
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* Add support for accessing whole struct
* Update tests
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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Add co-simulation in sim pass
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anlogic: support BRAM mapping
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Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.
Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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If a local variable is always assigned before it is used, then adding
nosync prevents latches from being needlessly generated.
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- Prevent unmatched expected error patterns from self-matching
- Prevent infinite recursion on unmatched expected warnings
- Always print the error message for unmatched error patterns
- Add test coverage for all unmatched message types
- Add test coverage for excess matched logs and warnings
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- add generated doubleslash.v to .gitignore
- ensure backend verilog can be read again
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Fixes #3117.
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I also removed the unnecessary shadowing of `width_hint` and `sign_hint`
in the corresponding case in `simplify()`.
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The preprocessor currently destroys double slash containing escaped
identifiers (for example \a//b ). This is due to next_token trying to
convert single line comments (//) into /* */ comments. This then leads
to an unintuitive error message like this:
ERROR: syntax error, unexpected '*'
This patch fixes the error by recognizing escaped identifiers and
returning them as single token. It also adds a testcase.
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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* remove `write_edif` and `write_blif` options
* remove redundant `abc` call before muxcover
* update style
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Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail.
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Signed-off-by: Patrick Urban <patrick.urban@web.de>
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- Attempt to lookup a derived module if it potentially contains a port
connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
connections in a future change
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Fixes #3047.
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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- FfData now keeps track of the module and underlying cell, if any (so
calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
compilation
- the "flip FF data sense by inserting inverters in front and after"
functionality that zinit uses is moved onto FfData class and beefed up
to have dffsr support, to support more use cases
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Fix "make vgtest"
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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This enables the usage of declarations of wand or wor with a base type
of logic, integer, or a typename. Note that declarations of nets with
2-state base types is still permitted, in violation of the spec.
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- Root AST_PREFIX nodes are now subject to genblk expansion to allow
them to refer to a locally-visible generate block
- Part selects on AST_PREFIX member leafs can now refer to generate
block items (previously would not resolve and raise an error)
- Add source location information to AST_PREFIX nodes
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* Add testcase
* Cleanup some state at end of abc9
* Re-assign abc9_box_id from scratch
* Suppress delete unless prep_bypass did something
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* Add testcase
* holes module to instantiate cells with NEW_ID
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* Add close bracket
* Add testcase
* Replace cell type/param if in unmap_design
* Improve abc9_box error message too
* Update comment as per review
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This is accomplished by generating a unique name for the genvar,
renaming references to the genvar only in the loop's initialization,
guard, and incrementation, and finally adding a localparam inside the
loop body with the original name so that the genvar can be shadowed as
expected.
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In line with other tools, this adds an extra wrapping block around such
for loops to appropriately scope the variable.
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Previously, opt_clean would reconnect all ports (including FF Q ports)
to a "canonical" SigBit chosen by complex rules, but would leave the
init attribute on the old wire. This change applies the same
canonicalization rules to the init attributes, ensuring that init moves
to wherever the Q port moved.
Part of another jab at #2920.
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