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* More fixes in ternary op sign handlingClifford Wolf2013-07-121-0/+8
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* Fixed sign handling in ternary operatorClifford Wolf2013-07-121-0/+8
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* Another vloghammer related bugfixClifford Wolf2013-07-111-0/+7
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* More fixes in ast expression sign/width handlingClifford Wolf2013-07-091-13/+15
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-07-092-2/+20
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| * Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-092-2/+20
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* | Fixed shift ops with large right hand sideClifford Wolf2013-07-091-3/+43
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* Fixed another bug found using vloghammerClifford Wolf2013-07-071-0/+10
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* Removed tests/xsthammerClifford Wolf2013-07-0713-1748/+0
| | | | | This test is now available as 'vloghammer' in a seperate repository: https://github.com/cliffordwolf/VlogHammer
* Fixed vivado related xsthammer bugsClifford Wolf2013-07-053-2/+14
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* Various improvements in xsthammer report generatorClifford Wolf2013-07-051-6/+23
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* Added work-around to isim bug in xsthammer report scriptClifford Wolf2013-07-051-4/+5
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* Added CARRY4 Xilinx cell to xsthammer cell libClifford Wolf2013-07-051-0/+13
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* Added xsthammer report generatorClifford Wolf2013-07-054-13/+170
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* Improved xsthammer quartus supportClifford Wolf2013-07-042-1/+484
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* Added Altera Cyclon III cell library to xsthammerClifford Wolf2013-07-043-14/+115
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* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-041-0/+16
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* Added Altera Quartus support to xsthammerClifford Wolf2013-07-033-2/+39
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* Progress in xsthammerClifford Wolf2013-07-035-9/+23
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* Added vivado support to xsthammerClifford Wolf2013-06-265-7/+69
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* Added timout functionality to SAT solverClifford Wolf2013-06-201-2/+2
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* Added "eval" passClifford Wolf2013-06-191-2/+2
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* Added more stuff to xsthammer, found first xst bugClifford Wolf2013-06-172-2/+175
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* Added ternary op and concat op to xsthammerClifford Wolf2013-06-151-7/+124
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* Added consteval testing to xsthammer and fixed bugsClifford Wolf2013-06-131-2/+7
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* More xsthammer improvements (using xst 14.5 now)Clifford Wolf2013-06-135-69/+49
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* Another fix for a bug found using xsthammerClifford Wolf2013-06-121-4/+8
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* Further improved and extended xsthammerClifford Wolf2013-06-116-138/+226
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* More xsthammer improvementsClifford Wolf2013-06-102-21/+27
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* Progress xsthammer scriptsClifford Wolf2013-06-103-27/+37
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* Progress in xsthammer: working proof for cell modelsClifford Wolf2013-06-103-34/+51
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* Progress on xsthammerClifford Wolf2013-06-105-0/+268
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* Added first xsthammer scriptsClifford Wolf2013-06-104-0/+183
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* Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.vClifford Wolf2013-05-241-1/+3
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* Removed test cases that have been moved to yosys-test.Clifford Wolf2013-05-1783-18963/+0
| | | | https://github.com/cliffordwolf/yosys-tests/
* Improved vcdcd.pl (added -d option)Clifford Wolf2013-05-141-8/+82
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* Some improvements in vcdcd.plClifford Wolf2013-05-141-4/+16
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* Fixed a bug in AST frontend for cases with non-blocking assigned variables ↵Clifford Wolf2013-04-131-0/+19
| | | | as case values
* Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-312-14/+1
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* Added test cases from 2012 paper on comparison of foss verilog synthesis toolsClifford Wolf2013-03-316-0/+111
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* Added k68 (m68k compatible cpu) test case from verilatorClifford Wolf2013-03-313-0/+61
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* Renamed hansimem.v test case to mem_arst.vClifford Wolf2013-03-241-1/+0
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* Added hansimem testcase (memory with async reset)Clifford Wolf2013-03-241-0/+44
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* Set execute bit on tests/openmsp430/run-synth.sh for realClifford Wolf2013-03-171-0/+0
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* set executable flags to run-synth.sh, added .gitignoreJohann Glaser2013-03-171-0/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* added ckeck for Icarus Verilog, otherwise the tests are silently stoppedJohann Glaser2013-03-171-0/+7
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* added more .gitignore files (make test)Clifford Wolf2013-01-054-0/+7
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* initial importClifford Wolf2013-01-05367-0/+28611
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