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| | | * | | Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2syncEddie Hung2019-10-082-9/+4
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| | | | * | | Disable equiv check for ice40 latchesEddie Hung2019-10-031-6/+3
| | | | * | | Use equiv_opt -async2sync for xilinxEddie Hung2019-10-031-3/+1
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| | | * | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolfEddie Hung2019-10-051-0/+22
| | * | | | hierarchy - proc reorderMiodrag Milanovic2019-10-189-14/+18
| | * | | | Check latches type one by oneMiodrag Milanovic2019-10-042-40/+25
| | * | | | Removed top module where not neededMiodrag Milanovic2019-10-044-37/+4
| | * | | | Test muxes synth one by oneMiodrag Milanovic2019-10-042-38/+39
| | * | | | Cleaned verilog code from not used definesMiodrag Milanovic2019-10-041-6/+0
| | * | | | Check for MULT18X18D, since that is working nowMiodrag Milanovic2019-10-042-14/+11
| | * | | | Check flops one by oneMiodrag Milanovic2019-10-044-71/+50
| | * | | | Removed alu and div_mod tests as agreedMiodrag Milanovic2019-10-044-57/+0
| | * | | | equiv_opt with -assertEddie Hung2019-09-301-3/+1
| | * | | | Update resource count for alu.ysEddie Hung2019-09-301-3/+3
| | * | | | Move $x to end as per 7f0eec8Eddie Hung2019-09-301-1/+1
| | * | | | Update fsm.ys resource countEddie Hung2019-09-301-3/+3
| | * | | | Merge branch 'SergeyDegtyar/ecp5' of https://github.com/SergeyDegtyar/yosys i...Eddie Hung2019-09-3036-0/+800
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| | | * | | Add comment to dpram test about related issue.SergeyDegtyar2019-09-181-0/+1
| | | * | | adffs test update (equiv_opt -multiclock). div_mod test fixSergeyDegtyar2019-09-173-17/+12
| | | * | | Remove stat command form shifter.ys testSergeyDegtyar2019-09-041-1/+1
| | | * | | Fix ecp5 testsSergeyDegtyar2019-09-0411-2421/+26
| | | * | | Uncomment sat command in memory.ys test.SergeyDegtyar2019-09-031-2/+1
| | | * | | Add tests for ECP5 architectureSergeyDegtyar2019-09-0339-0/+3200
| * | | | | hierarchy - proc reorderMiodrag Milanovic2019-10-184-9/+10
| * | | | | Cleanup and formatingMiodrag Milanovic2019-10-044-2/+4
| * | | | | split latches into separate checksMiodrag Milanovic2019-10-042-41/+24
| * | | | | check muxes per typeMiodrag Milanovic2019-10-042-42/+37
| * | | | | check ff's separatelyMiodrag Milanovic2019-10-042-26/+14
| * | | | | Cleanup top modules and not used definesMiodrag Milanovic2019-10-045-44/+5
| * | | | | remove alu testMiodrag Milanovic2019-10-042-36/+0
| * | | | | Merge branch 'SergeyDegtyar/anlogic' of https://github.com/SergeyDegtyar/yosy...Miodrag Milanovic2019-10-0422-0/+535
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| | * | | | Merge branch 'master' into SergeyDegtyar/anlogicSergey2019-10-0134-55/+1053
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| | * | | | run-test.sh Move $x at end of line.Sergey2019-10-011-1/+1
| | * | | | Add new tests for Anlogic architectureSergeyDegtyar2019-09-2322-0/+535
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* | | | | hierarchy - proc reorderMiodrag Milanovic2019-10-186-13/+15
* | | | | Split mux tests per typeMiodrag Milanovic2019-10-042-38/+36
* | | | | Split latch checkMiodrag Milanovic2019-10-042-45/+24
* | | | | split rest od ff'sMiodrag Milanovic2019-10-043-30/+17
* | | | | Separate check for ff's typesMiodrag Milanovic2019-10-042-47/+48
* | | | | Cleaned testsMiodrag Milanovic2019-10-045-49/+4
* | | | | Remove not needed testsMiodrag Milanovic2019-10-046-75/+0
* | | | | Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys...Miodrag Milanovic2019-10-0430-0/+709
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| * | | | run-test.sh Move $x at end of line.Sergey2019-10-011-1/+1
| * | | | Merge branch 'master' into SergeyDegtyar/efinixSergey2019-10-0134-55/+1053
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| * | | | Add new tests for Efinix architecture.SergeyDegtyar2019-09-2330-0/+709
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* | | | Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-031-0/+10
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| * | | Add quick testEddie Hung2019-09-301-0/+10
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* | | Extend test with renaming cells with prefix tooEddie Hung2019-10-021-0/+2
* | | Add testEddie Hung2019-09-301-0/+16
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* | Merge pull request #1406 from whitequark/connect_rpcwhitequark2019-09-306-0/+152
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