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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 19:54:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 19:54:59 -0700 |
| commit | 1caaf5149258ff84ac2a6532c26e9ffb076183a9 (patch) | |
| tree | 59c25bda0fc04943d5671280d9dc66c2b2ef4b24 /tests | |
| parent | f8d5e11aa7285fc92832b87063d530afe27eca28 (diff) | |
| download | yosys-1caaf5149258ff84ac2a6532c26e9ffb076183a9.tar.gz yosys-1caaf5149258ff84ac2a6532c26e9ffb076183a9.tar.bz2 yosys-1caaf5149258ff84ac2a6532c26e9ffb076183a9.zip | |
equiv_opt with -assert
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/ecp5/fsm.ys | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys index 36b10c0ce..6368edc57 100644 --- a/tests/ecp5/fsm.ys +++ b/tests/ecp5/fsm.ys @@ -2,9 +2,7 @@ read_verilog fsm.v hierarchy -top top proc flatten -#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:L6MUX21 |