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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 08:45:58 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 08:45:58 +0200 |
| commit | d6ef9b1a6b47e740dba948e5f2fcf456d7ee79cf (patch) | |
| tree | a0025fa53f8b0e223da0283aad27bbf4cb15748d /tests | |
| parent | abb5a3a44df18a6ca18b6998f4c35aafc4284df8 (diff) | |
| download | yosys-d6ef9b1a6b47e740dba948e5f2fcf456d7ee79cf.tar.gz yosys-d6ef9b1a6b47e740dba948e5f2fcf456d7ee79cf.tar.bz2 yosys-d6ef9b1a6b47e740dba948e5f2fcf456d7ee79cf.zip | |
Cleaned verilog code from not used defines
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/ecp5/shifter.v | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/tests/ecp5/shifter.v b/tests/ecp5/shifter.v index c55632552..04ae49d83 100644 --- a/tests/ecp5/shifter.v +++ b/tests/ecp5/shifter.v @@ -9,14 +9,8 @@ in always @(posedge clk)
begin
-`ifndef BUG
out <= out >> 1;
out[7] <= in;
-`else
-
- out <= out << 1;
- out[7] <= in;
-`endif
end
endmodule
|