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* Moved all tests in arch sub directoryMiodrag Milanovic2019-10-1836-1034/+0
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* hierarchy - proc reorderMiodrag Milanovic2019-10-1810-17/+21
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* Make equivalence work with latest masterMiodrag Milanovic2019-10-173-8/+8
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* remove not needed top moduleMiodrag Milanovic2019-10-172-20/+2
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* remove not needed top moduleMiodrag Milanovic2019-10-172-17/+2
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* split muxes synth per typeMiodrag Milanovic2019-10-172-39/+39
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* Test dffs separetelyMiodrag Milanovic2019-10-172-26/+19
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* Split latches into separete testsMiodrag Milanovic2019-10-172-42/+27
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* Fix formattingMiodrag Milanovic2019-10-171-1/+8
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* Clean verilog code from not used define blockMiodrag Milanovic2019-10-172-12/+0
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* Removed alu and div_mod test as agreed, ignore generated filesMiodrag Milanovic2019-10-175-70/+1
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* Test per flip-flop typeMiodrag Milanovic2019-10-172-47/+37
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* Add -assertEddie Hung2019-10-171-1/+1
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* Use built-in async2sync call as per #1417Eddie Hung2019-10-171-4/+0
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* Update mul test to DSP48E1Eddie Hung2019-10-171-9/+2
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* Update area for div_modEddie Hung2019-10-171-6/+6
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* Add comment for lack of tristate logic pointing to #1225Eddie Hung2019-10-171-1/+1
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* Move $x to end as 7f0eec8Eddie Hung2019-10-171-1/+1
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* adffs test update (equiv_opt -multiclock)SergeyDegtyar2019-10-171-5/+6
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* Fix div_mod testSergey2019-10-171-1/+1
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* Fix div_mod testSergey2019-10-171-1/+1
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* Fix div_mod testSergey2019-10-171-1/+1
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* Fix div_mod testSergey2019-10-171-1/+1
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* Fix div_mod testSergey2019-10-171-1/+1
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* Fix div_mod testSergey2019-10-171-1/+1
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* Add comment with expected behavior for latches,tribuf tests;Update adffs testSergeyDegtyar2019-10-174-14/+11
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* Fix latches.ys testSergeyDegtyar2019-10-171-4/+3
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* Add smoke tests to tests/xilinxSergeyDegtyar2019-10-1729-9/+654
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* Use equiv_opt -async2sync for xilinxEddie Hung2019-10-031-3/+1
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* Add latch test modified from #1363Eddie Hung2019-09-302-0/+73
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* Add mac.sh and macc_tb.v for testingEddie Hung2019-09-192-0/+99
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* Remove statEddie Hung2019-09-181-1/+0
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* Add .gitignoreEddie Hung2019-09-181-0/+1
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* Refine macc testcaseEddie Hung2019-09-182-9/+17
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* Add AREG=2 BREG=2 testEddie Hung2019-09-111-2/+6
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* Update test with a/b resetEddie Hung2019-09-111-2/+4
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* Extend test for RSTP and RSTMEddie Hung2019-09-112-3/+50
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* Add SIMD testEddie Hung2019-09-091-0/+25
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* Update macc testEddie Hung2019-09-062-42/+42
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* Add macc test, with equiv_opt not currently passingEddie Hung2019-08-302-0/+54
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* Update test for ffMEddie Hung2019-08-301-2/+2
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* Add mul_unsigned testEddie Hung2019-08-302-0/+41
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* Add .gitignoreEddie Hung2019-08-281-0/+3
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* Use test_pmgen for xilinx_srlEddie Hung2019-08-281-0/+57
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* Do not simplemap for variable testEddie Hung2019-08-281-2/+2
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* Add xilinx_srl testEddie Hung2019-08-283-0/+127