diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-03 10:30:33 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-03 10:30:33 -0700 |
| commit | 5d680590d6bccd929ed3909248dbb73fb3876e65 (patch) | |
| tree | bdeb9cf671fc44ac44b281bc36c3a99ea9fc64b7 /tests/xilinx | |
| parent | 8765ec3c27f38e6fb57d057be9605788e144388b (diff) | |
| download | yosys-5d680590d6bccd929ed3909248dbb73fb3876e65.tar.gz yosys-5d680590d6bccd929ed3909248dbb73fb3876e65.tar.bz2 yosys-5d680590d6bccd929ed3909248dbb73fb3876e65.zip | |
Use equiv_opt -async2sync for xilinx
Diffstat (limited to 'tests/xilinx')
| -rw-r--r-- | tests/xilinx/latches.ys | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index ac1102896..bd1dffd21 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -2,9 +2,7 @@ read_verilog latches.v proc flatten -equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -async2sync -equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load preopt synth_xilinx |