Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | opt_mem: Remove constant-value bit lanes. | Marcelina KoĆcielnicka | 2022-05-07 | 1 | -15/+1 |
| | |||||
* | Fix the tests we just broke | Claire Xenia Wolf | 2021-12-10 | 1 | -1/+1 |
| | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | ||||
* | tests: Centralize test collection and Makefile generation | Xiretza | 2020-09-21 | 1 | -1/+1 |
| | |||||
* | Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh | Clifford Wolf | 2014-03-11 | 1 | -1/+1 |
| | |||||
* | Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog) | Clifford Wolf | 2014-03-11 | 1 | -1/+1 |
| | |||||
* | Added tests/techmap/mem_simple_4x1 | Clifford Wolf | 2014-02-21 | 1 | -0/+17 |