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| author | Claire Xenia Wolf <claire@clairexen.net> | 2021-12-10 00:22:37 +0100 |
|---|---|---|
| committer | Claire Xenia Wolf <claire@clairexen.net> | 2021-12-10 00:22:37 +0100 |
| commit | d6e4d3f1ba9191f0f3bbed2d47a9ef80b8614e77 (patch) | |
| tree | ce3d60c7aa65c8f67a583f1d8da1913ade20fd9e /tests/techmap/mem_simple_4x1_runtest.sh | |
| parent | ce08046f4439575f551449e00b502717459bee63 (diff) | |
| download | yosys-d6e4d3f1ba9191f0f3bbed2d47a9ef80b8614e77.tar.gz yosys-d6e4d3f1ba9191f0f3bbed2d47a9ef80b8614e77.tar.bz2 yosys-d6e4d3f1ba9191f0f3bbed2d47a9ef80b8614e77.zip | |
Fix the tests we just broke
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
Diffstat (limited to 'tests/techmap/mem_simple_4x1_runtest.sh')
| -rw-r--r-- | tests/techmap/mem_simple_4x1_runtest.sh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh index 9c41fa56a..b486de5c7 100644 --- a/tests/techmap/mem_simple_4x1_runtest.sh +++ b/tests/techmap/mem_simple_4x1_runtest.sh @@ -2,7 +2,7 @@ set -e -../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v +../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'read_verilog mem_simple_4x1_uut.v; proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v |