| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | opt_mem: Remove constant-value bit lanes. | Marcelina Kościelnicka | 2022-05-07 | 1 | -15/+1 |
| * | Fix the tests we just broke | Claire Xenia Wolf | 2021-12-10 | 1 | -1/+1 |
| * | tests: Centralize test collection and Makefile generation | Xiretza | 2020-09-21 | 1 | -1/+1 |
| * | Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh | Clifford Wolf | 2014-03-11 | 1 | -1/+1 |
| * | Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog) | Clifford Wolf | 2014-03-11 | 1 | -1/+1 |
| * | Added tests/techmap/mem_simple_4x1 | Clifford Wolf | 2014-02-21 | 1 | -0/+17 |
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index : iCE40/yosys | |
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