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* Fixed bug with memories that do not have a down-to-zero data widthClifford Wolf2016-08-221-0/+30
* Added another mem2reg test caseClifford Wolf2016-08-211-0/+11
* Another bugfix in mem2reg codeClifford Wolf2016-08-211-0/+22
* Fixed mem assignment in left-hand-side concatenationClifford Wolf2016-07-081-0/+13
* Fixed init issue in mem2reg_test2 test caseClifford Wolf2016-06-171-2/+6
* Added opt_expr support for div/mod by power-of-twoClifford Wolf2016-05-291-0/+27
* Bugfix and improvements in memory_shareClifford Wolf2016-04-211-0/+21
* Added tests/simple/graphtest.vClifford Wolf2015-11-301-0/+34
* More bugfixes in handling of parameters in tasks and functionsClifford Wolf2015-11-121-1/+12
* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-111-1/+30
* Bugfix in memory_dffClifford Wolf2015-10-311-0/+15
* Improvements in wreduceClifford Wolf2015-10-311-0/+9
* Another block of spelling fixesLarry Doolittle2015-08-144-6/+6
* Fixed trailing whitespacesClifford Wolf2015-07-023-6/+6
* Various fixes for memories with offsetsClifford Wolf2015-02-141-2/+2
* Added $meminit support to "memory" commandClifford Wolf2015-02-141-15/+8
* Added $meminit test caseClifford Wolf2015-02-141-0/+30
* improvements in muxtree/select_leaves testClifford Wolf2015-01-181-2/+5
* Improvements in opt_muxtreeClifford Wolf2015-01-181-0/+8
* Added support for task and function args in parenthesesClifford Wolf2014-10-271-1/+35
* Added multi-dim memory test (requires iverilog git head)Clifford Wolf2014-08-121-0/+11
* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-051-0/+63
* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-051-0/+13
* Added "make -j{N}" support to "make test"Clifford Wolf2014-07-301-1/+1
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-281-0/+57
* Renamed some of the test cases in tests/simple to avoid name collisionsClifford Wolf2014-07-2515-30/+30
* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-171-1/+40
* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-171-0/+21
* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-171-0/+20
* Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-161-1/+1
* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-021-0/+7
* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-251-3/+6
* Little steps in realmath test benchClifford Wolf2014-06-211-0/+6
* Added test case for AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-171-0/+12
* Removed long running tests from tests/simple/realexpr.v (replaced by tests/re...Clifford Wolf2014-06-151-55/+0
* Added tests/realmath to "make test"Clifford Wolf2014-06-151-1/+0
* Added support for math functionsClifford Wolf2014-06-141-0/+57
* Added realexpr.v test caseClifford Wolf2014-06-141-0/+13
* added tests for new verilog featuresClifford Wolf2014-06-072-6/+37
* Added tests/simple/repwhile.vClifford Wolf2014-06-061-0/+20
* Progress in Verific bindingsClifford Wolf2014-03-172-1/+4
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-0/+39
* Bugfix in name resolution with generate blocksClifford Wolf2014-01-301-0/+24
* Added correct handling of $memwr priorityClifford Wolf2014-01-031-0/+17
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-271-0/+11
* Added multiplier test case from eda playgroundClifford Wolf2013-12-181-0/+132
* Added elsif preproc supportClifford Wolf2013-12-181-1/+229
* Added support for macro argumentsClifford Wolf2013-12-181-0/+9
* Various improvements in support for generate statementsClifford Wolf2013-12-041-0/+27
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-041-1/+1
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