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| author | Clifford Wolf <clifford@clifford.at> | 2014-06-17 21:49:59 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-06-17 21:49:59 +0200 |
| commit | df76da8fd710394e7ea999e90994483da223f545 (patch) | |
| tree | d71eb9154a590335d78fec7bca2d6da996409996 /tests/simple | |
| parent | 80e459469576b82975a5cf663b4aba2e044d9476 (diff) | |
| download | yosys-df76da8fd710394e7ea999e90994483da223f545.tar.gz yosys-df76da8fd710394e7ea999e90994483da223f545.tar.bz2 yosys-df76da8fd710394e7ea999e90994483da223f545.zip | |
Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/mem2reg.v | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v index e2c136ddb..3630b57c7 100644 --- a/tests/simple/mem2reg.v +++ b/tests/simple/mem2reg.v @@ -43,3 +43,15 @@ end endmodule +// ------------------------------------------------------ + +// http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/ +module test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b); +reg [7:0] dint_c [0:7]; +always @(posedge clk) + begin + {dout_a[0], dint_c[3]} <= din_a; + end +assign dout_b = dint_c[3]; +endmodule + |