| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. | Marcelina Kościelnicka | 2021-08-11 | 1 | -51/+102 |
| * | Add v2 memory cells. | Marcelina Kościelnicka | 2021-08-11 | 1 | -17/+17 |
| * | tests: remove write_ilang | Eddie Hung | 2020-04-20 | 1 | -2/+0 |
| * | ecp5: do not map FFRAM if explicitly requested otherwise. | whitequark | 2020-04-03 | 1 | -16/+62 |
| * | ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. | whitequark | 2020-02-06 | 1 | -0/+284 |
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index : iCE40/yosys | |
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