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* Proper example codeMiodrag Milanovic2022-03-142-1/+3
* Bump versiongithub-actions[bot]2022-03-121-1/+1
* Merge pull request #3229 from YosysHQ/micko/sim_dateMiodrag Milanović2022-03-111-7/+20
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| * Add date parameter to enable full date/time and version infoMiodrag Milanovic2022-03-111-7/+20
* | Merge pull request #3222 from zachjs/prune-linux-ciMiodrag Milanović2022-03-111-2/+6
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| * | Prune Linux CI buildsZachary Snow2022-03-111-2/+6
* | | Merge pull request #3228 from YosysHQ/micko/disable_testsMiodrag Milanović2022-03-112-28/+2
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| * | | Disable tests on most of platformsMiodrag Milanovic2022-03-102-28/+2
* | | | Add "sim -q" optionClaire Xenia Wolf2022-03-111-8/+19
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* | | Small fix in "sim" help messageClaire Xenia Wolf2022-03-111-1/+1
* | | Merge pull request #3226 from YosysHQ/micko/btor2witnessMiodrag Milanović2022-03-112-10/+171
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| * | FstData already do conversion to VCDMiodrag Milanovic2022-03-111-1/+2
| * | Support cell name in btor witness fileMiodrag Milanovic2022-03-111-5/+14
| * | Fix handling of some formal cells in btor back-endClaire Xenia Wolf2022-03-111-6/+2
| * | handle state names of $anyconst and $anyseqMiodrag Milanovic2022-03-111-1/+5
| * | Proper write of memory dataMiodrag Milanovic2022-03-111-14/+13
| * | Start work on memory initMiodrag Milanovic2022-03-091-9/+34
| * | Fixes and error checkMiodrag Milanovic2022-03-091-1/+5
| * | cleanupMiodrag Milanovic2022-03-071-1/+2
| * | Error checks for aiger witnessMiodrag Milanovic2022-03-071-0/+7
| * | btor2 witness co-simulationMiodrag Milanovic2022-03-071-8/+123
* | | Bump versiongithub-actions[bot]2022-03-101-1/+1
* | | intel_alm: M10K write-enable is negative-trueLofty2022-03-097-8/+30
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* | Merge pull request #3210 from rqou/json-signedMiodrag Milanović2022-03-071-0/+2
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| * json: Add help message for `signed` fieldR2022-02-211-0/+2
* | Bump versiongithub-actions[bot]2022-03-051-1/+1
* | Merge pull request #3186 from nakengelhardt/smtbmc_sby_print_idMiodrag Milanović2022-03-042-4/+12
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| * | print cell name for properties in yosys-smtbmcN. Engelhardt2022-02-222-4/+12
* | | Merge pull request #3206 from YosysHQ/micko/quote_removeMiodrag Milanović2022-03-041-1/+4
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| * | | Remove quotes if any from attributeMiodrag Milanovic2022-02-161-1/+4
* | | | Merge pull request #3207 from nakengelhardt/json_escape_quotesMiodrag Milanović2022-03-045-5/+63
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| * | | | fix handling of escaped chars in json backend and frontendN. Engelhardt2022-02-185-5/+63
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* | | | Next dev cycleMiodrag Milanovic2022-03-042-2/+5
* | | | Release version 0.15Miodrag Milanovic2022-03-042-3/+3
* | | | Update ABCMiodrag Milanovic2022-03-041-1/+1
* | | | Update documentationMiodrag Milanovic2022-03-041-1/+96
* | | | Merge pull request #3219 from YosysHQ/micko/quick_vcdMiodrag Milanović2022-03-043-0/+21
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| * | | | VCD reader support by using external toolMiodrag Milanovic2022-02-283-0/+21
* | | | | Merge pull request #3220 from YosysHQ/claire/simstuffMiodrag Milanović2022-03-041-141/+301
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| * | | | | Add option to ignore X only signals in outputMiodrag Milanovic2022-03-021-8/+32
| * | | | | Write simulation files after simulation is performedMiodrag Milanovic2022-03-021-145/+151
| * | | | | Merge pull request #3224 from YosysHQ/micko/refactorClaire Xen2022-03-021-213/+254
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| | * | | | | CleanupMiodrag Milanovic2022-03-021-10/+7
| | * | | | | Refactor sim output writersMiodrag Milanovic2022-02-281-213/+257
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| * | | | | Quick fixMiodrag Milanovic2022-02-281-0/+2
| * | | | | Add writing of aiw files to "sim" commandClaire Xenia Wolf2022-02-281-1/+87
| * | | | | Hotfix in AIGER witness reader state machineClaire Xenia Wolf2022-02-281-0/+1
* | | | | | Bump versiongithub-actions[bot]2022-03-031-1/+1
* | | | | | Update CHANGELOGMiodrag Milanovic2022-03-021-0/+12
* | | | | | Bump versiongithub-actions[bot]2022-03-011-1/+1
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