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* Improved xilinx mojo_counter exampleClifford Wolf2013-10-262-2/+5
* Added another xilinx example (not funcional yet)Clifford Wolf2013-10-264-0/+101
* Bugfix in dffsr techmap rulesClifford Wolf2013-10-181-8/+8
* Added techmap rules for $sr, $dffsr and $dlatchClifford Wolf2013-10-181-0/+181
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-181-0/+166
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-181-20/+76
* Added map, par and bitgen to xlinx7 exampleClifford Wolf2013-10-161-2/+39
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-156-7/+7
* Added spice testbench to techlibs/cmosClifford Wolf2013-09-144-3/+73
* Added spice backendClifford Wolf2013-09-144-0/+78
* Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)Clifford Wolf2013-08-271-2/+10
* Added simple xilinx7 technology mapping filesClifford Wolf2013-08-224-0/+167
* Implemented same div-by-zero behavior as found in other synthesis toolsClifford Wolf2013-08-151-2/+31
* Added $div and $mod technology mappingClifford Wolf2013-08-091-9/+93
* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-231-0/+32
* Fixed shift ops with large right hand sideClifford Wolf2013-07-091-6/+6
* More fixes for bugs found using xsthammerClifford Wolf2013-06-131-8/+7
* More sign-extension related fixesClifford Wolf2013-06-101-12/+13
* Implemented technology mapping for multipliers (using array multiplier)Clifford Wolf2013-06-031-4/+30
* Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.vClifford Wolf2013-04-071-4/+4
* Added EXTRA_TARGETS Makefile variableClifford Wolf2013-03-281-1/+1
* Tiny bugfix in simlib.vClifford Wolf2013-03-261-1/+0
* Fixed stdcells.v for $adff with undef reset valueClifford Wolf2013-03-241-63/+68
* More support code for $sr cellsClifford Wolf2013-03-141-0/+21
* added .gitignore filesClifford Wolf2013-01-051-0/+1
* initial importClifford Wolf2013-01-055-0/+2447