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| | * | | Fixes for 2:1 muxesEddie Hung2019-07-082-5/+30
| | * | | synth_xilinx -widemux=2 is minimum nowEddie Hung2019-07-081-4/+7
| | * | | Parametric muxcover costs as per @daveshah1Eddie Hung2019-07-081-16/+14
| | * | | atoi -> stoi as per @daveshah1Eddie Hung2019-07-081-1/+1
| * | | | synth_ecp5: Fix typo in copyright headerDavid Shah2019-07-091-1/+1
| * | | | Revert "Add "synth -keepdc" option"Eddie Hung2019-07-091-13/+2
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| * | | Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanupClifford Wolf2019-07-091-19/+25
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| | * \ \ Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanupEddie Hung2019-07-022-0/+3
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| | * | | | Cleanup SRL inference/make more consistentEddie Hung2019-06-291-19/+25
| * | | | | Merge pull request #1166 from YosysHQ/eddie/synth_keepdcEddie Hung2019-07-081-2/+13
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| | * | | | Add synth -keepdc optionEddie Hung2019-07-081-2/+13
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| * / | | synth_intel: Warn about untested Quartus backendDan Ravensloft2019-07-071-0/+3
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* | | | xc7: Map combinational DSP48E1sDavid Shah2019-07-084-7/+77
* | | | mul2dsp: Fix typoDavid Shah2019-07-081-1/+1
* | | | Add mul2dsp multiplier splitting rule and ECP5 mappingDavid Shah2019-07-085-2/+280
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* | | Fix $__XILINX_MUXF78 box timingEddie Hung2019-07-011-1/+1
* | | Revert "Fix broken MUXFx box, use MUXF7x2 box instead"Eddie Hung2019-07-013-37/+36
* | | Fix broken MUXFx box, use MUXF7x2 box insteadEddie Hung2019-07-013-36/+37
* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-293-16/+9
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| * | install *_nowide.lut filesEddie Hung2019-06-292-0/+3
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| * Remove peepopt call in synth_xilinx since already in synth -run coarseEddie Hung2019-06-281-5/+0
* | Restore $__XILINX_MUXF78 const optimisationEddie Hung2019-06-281-24/+24
* | Clean up trimming leading 1'bx in A during techmappnigEddie Hung2019-06-281-15/+9
* | Fix CARRY4 abc_box_idEddie Hung2019-06-281-1/+1
* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-287-26/+13
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| * Update synth_ice40 -device doc to be relevant for -abc9 onlyEddie Hung2019-06-281-2/+2
| * Disable boxing of ECP5 dist RAM due to regressionEddie Hung2019-06-281-1/+1
| * Add write address to abc_scc_break of ECP5 dist RAMEddie Hung2019-06-281-1/+1
| * Fix DO4 typoEddie Hung2019-06-281-1/+1
| * Reduce diff with upstreamEddie Hung2019-06-271-4/+2
| * Extraneous newlineEddie Hung2019-06-271-1/+0
| * Remove noise from ice40/cells_sim.vEddie Hung2019-06-271-5/+0
| * Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-273-9/+7
| * Remove redundant docEddie Hung2019-06-271-3/+0
* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-271-7/+10
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| * Add warning if synth_xilinx -abc9 with family != xc7Eddie Hung2019-06-271-0/+2
| * Merge origin/masterEddie Hung2019-06-274-51/+100
* | MUXF78 -> $__MUXF78 to indicate internalEddie Hung2019-06-261-1/+1
* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-264-8/+10
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| * Add WE to ECP5 dist RAM's abc_scc_break tooEddie Hung2019-06-261-1/+1
| * Update comment on boxesEddie Hung2019-06-262-4/+6
| * Add "WE" to dist RAM's abc_scc_breakEddie Hung2019-06-261-3/+3
* | synth_xilinx's muxcover call to be very conservative -- -nodecodeEddie Hung2019-06-261-1/+1
* | Accidentally removed "simplemap $mux"Eddie Hung2019-06-261-0/+1
* | Replace with <internal options>Eddie Hung2019-06-261-2/+2
* | Rework help_mode for synth_xilinx -widemuxEddie Hung2019-06-261-22/+23
* | Return to upstream synth_xilinx with opt -full and wreduceEddie Hung2019-06-261-19/+3
* | Merge remote-tracking branch 'origin/eddie/fix1132' into xc7muxEddie Hung2019-06-263-44/+92
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| * | Simulation model verilog fixMiodrag Milanovic2019-06-262-14/+1
| * | Add more ECP5 Diamond flip-flops.whitequark2019-06-262-30/+91
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