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| author | David Shah <dave@ds0.me> | 2019-07-08 15:43:48 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-07-08 18:42:41 +0100 |
| commit | e78864993adab41492670c089f6365088426726f (patch) | |
| tree | a9d2ee76015839dc9bc19383644996e7d67c75d0 /techlibs | |
| parent | 269ff450f55f4354c82db1b98f8eb722317d9250 (diff) | |
| download | yosys-e78864993adab41492670c089f6365088426726f.tar.gz yosys-e78864993adab41492670c089f6365088426726f.tar.bz2 yosys-e78864993adab41492670c089f6365088426726f.zip | |
mul2dsp: Fix typo
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 37ce2e485..ece45db79 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -227,7 +227,7 @@ module \$__mul_gen (A, B, Y); if (Y_WIDTH < A_WIDTH+B_WIDTH)
assign Y = out[Y_WIDTH-1:0];
else begin
- wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+BWIDTH-1] : 1'b0);
+ wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+B_WIDTH-1] : 1'b0);
assign Y = { {{Y_WIDTH-(A_WIDTH+B_WIDTH)}{Ysign}}, out[A_WIDTH+B_WIDTH-1:0] };
end
end
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