aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Collapse)AuthorAgeFilesLines
* Ohmilord this wasn't added all this time!?!Eddie Hung2019-10-041-0/+29
|
* ecp5: Fix shuffle_enable portDavid Shah2019-10-011-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for mapping 36-bit wide PDP BRAMsDavid Shah2019-10-016-1/+183
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-306-122/+46
|
* synth_xilinx: Support latches, remove used-up FF init values.Marcin Kościelnicki2019-09-302-2/+76
| | | | Fixes #1387.
* Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2919-31/+3395
|\ | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5)
| * Re-orderEddie Hung2019-09-272-2/+2
| |
| * Missing (* mul2dsp *) for sliceBEddie Hung2019-09-271-2/+2
| |
| * Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run onceEddie Hung2019-09-261-9/+4
| |
| * TypoEddie Hung2019-09-261-1/+1
| |
| * select onceEddie Hung2019-09-262-8/+12
| |
| * Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-263-38/+14
| |
| * mul2dsp.v slice namesEddie Hung2019-09-251-5/+5
| |
| * Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicitEddie Hung2019-09-251-3/+1
| |
| * Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"Eddie Hung2019-09-251-2/+6
| | | | | | | | This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1.
| * Revert "No need for $__mul anymore?"Eddie Hung2019-09-251-8/+8
| | | | | | | | This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827.
| * Only wreduce on t:$addEddie Hung2019-09-251-1/+1
| |
| * Remove _TECHMAP_CELLTYPE_ check since all $mulEddie Hung2019-09-251-6/+2
| |
| * No need for $__mul anymore?Eddie Hung2019-09-251-8/+8
| |
| * Call 'wreduce' after mul2dsp to avoid unextend()Eddie Hung2019-09-251-0/+1
| |
| * Oops. Actually use __NAME__ in ABC_DSP48E1 macroEddie Hung2019-09-251-1/+1
| |
| * Add (* techmap_autopurge *) to abc_unmap.v tooEddie Hung2019-09-231-11/+11
| |
| * Add techmap_autopurge to outputs in abc_map.v tooEddie Hung2019-09-231-11/+11
| |
| * Revert "Add a xilinx_finalise pass"Eddie Hung2019-09-233-87/+0
| | | | | | | | This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405.
| * Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"Eddie Hung2019-09-231-38/+38
| | | | | | | | This reverts commit 67c2db3486a7b2ff34f89dc861fb66d51ba6101b.
| * Revert "Vivado does not like zero width port connections"Eddie Hung2019-09-231-2/+2
| | | | | | | | This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98.
| * Vivado does not like zero width port connectionsEddie Hung2019-09-231-2/+2
| |
| * Remove (* techmap_autopurge *) from abc_unmap.v since no effectEddie Hung2019-09-231-38/+38
| |
| * Add a xilinx_finalise passEddie Hung2019-09-233-0/+87
| |
| * GrammarEddie Hung2019-09-201-1/+1
| |
| * Fix signedness bugEddie Hung2019-09-201-2/+2
| |
| * Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40Eddie Hung2019-09-202-3/+2
| |
| * Revert "Move mul2dsp before wreduce"Eddie Hung2019-09-201-4/+5
| | | | | | | | This reverts commit e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab.
| * Move mul2dsp before wreduceEddie Hung2019-09-201-5/+4
| |
| * Tidy up, fix undrivenEddie Hung2019-09-191-32/+34
| |
| * $__ABC_REG to have WIDTH parameterEddie Hung2019-09-192-17/+18
| |
| * Fix DSP48E1 timing by breaking P path if MREG or PREGEddie Hung2019-09-194-349/+363
| |
| * Revert "Different approach to timing"Eddie Hung2019-09-194-195/+405
| | | | | | | | This reverts commit 41256f48a5f3231e231cbdf9380a26128f272044.
| * Different approach to timingEddie Hung2019-09-194-405/+195
| |
| * Suppress $anyseq warningsEddie Hung2019-09-191-15/+32
| |
| * Use (* techmap_autopurge *) to suppress techmap warningsEddie Hung2019-09-192-94/+99
| |
| * D is 25 bits not 24 bits wideEddie Hung2019-09-191-1/+1
| |
| * Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dspEddie Hung2019-09-198-90/+502
| |\
| * | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2Eddie Hung2019-09-191-1/+4
| | |
| * | Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2Eddie Hung2019-09-191-1/+3
| | |
| * | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-189-948/+19414
| |\ \
| * | | Fix copy-pasteEddie Hung2019-09-181-2/+2
| | | |
| * | | Mis-spellEddie Hung2019-09-181-10/+25
| | | |
| * | | Add pattern detection support for DSP48E1 model, check against vendorEddie Hung2019-09-183-8/+102
| | | |
| * | | Add `undef DSP48E1_INSTEddie Hung2019-09-131-4/+5
| | | |
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 16:35:36 +0000