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* Add support for Xilinx PS7 blockEddie Hung2018-11-102-0/+624
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* Fix sf2 LUT interfaceClifford Wolf2018-10-312-12/+12
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Basic SmartFusion2 and IGLOO2 synthesis supportClifford Wolf2018-10-315-0/+377
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* ecp5: Remove DSP parameters that don't workDavid Shah2018-10-221-21/+0
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Add DSP blackboxesDavid Shah2018-10-213-1/+118
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Sim model fixesDavid Shah2018-10-191-3/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add latch inferenceDavid Shah2018-10-193-3/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #657 from mithro/xilinx-vprClifford Wolf2018-10-181-3/+2
|\ | | | | xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
| * xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.Tim 'mithro' Ansell2018-10-081-3/+2
| | | | | | | | | | Then if targeting vpr map all the Xilinx specific LUTs back into generic Yosys LUTs.
* | ecp5: Disable LSR inversionDavid Shah2018-10-162-21/+21
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | BRAM improvementsDavid Shah2018-10-121-11/+16
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Adding BRAM maps for all size optionsDavid Shah2018-10-101-1/+64
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: First BRAM type maps successfullyDavid Shah2018-10-108-10/+76
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Script for BRAM IO connectionsDavid Shah2018-10-104-64/+115
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Adding BRAM initialisation and configDavid Shah2018-10-095-0/+73
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Add blackbox for DP16KDDavid Shah2018-10-051-0/+93
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Add inout ports to cells_xtra.vClifford Wolf2018-10-042-2/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-031-0/+1
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* Merge pull request #645 from daveshah1/ecp5_dram_fixClifford Wolf2018-10-021-0/+1
|\ | | | | ecp5: Don't map ROMs to DRAM
| * ecp5: Don't map ROMs to DRAMDavid Shah2018-10-011-0/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Add iCE40 SB_SPRAM256KA simulation modelClifford Wolf2018-09-101-9/+30
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-2016-54/+54
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* ecp5: Fixing miscellaneous sim model issuesDavid Shah2018-07-161-2/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fixing 'X' issues with LUT simulation modelsDavid Shah2018-07-161-6/+19
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: ECP5 synthesis fixesDavid Shah2018-07-163-15/+32
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Adding synchronous set/reset supportDavid Shah2018-07-142-21/+42
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Add DRAM match ruleDavid Shah2018-07-131-0/+4
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Cells and mappings fixesDavid Shah2018-07-132-5/+5
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fixing arith_mapDavid Shah2018-07-131-4/+5
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Initial arith_map implementationDavid Shah2018-07-133-6/+80
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Adding basic synth_ecp5 based on synth_ice40David Shah2018-07-133-7/+345
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Adding DFF mapsDavid Shah2018-07-132-1/+30
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Adding DRAM mapDavid Shah2018-07-133-1/+76
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7David Shah2018-07-132-0/+473
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LCDavid Shah2018-07-131-2/+6
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add "synth_ice40 -json"Clifford Wolf2018-06-131-9/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix ice40_opt for cases where a port is connected to a signal with width != 1Clifford Wolf2018-06-111-9/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make -nordff the default in "prep"Clifford Wolf2018-05-301-9/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Avoid mixing module port declaration styles in ice40 cells_sim.vOlof Kindgren2018-05-171-43/+23
| | | | | | The current code requires workarounds for several simulators For modelsim, the file must be compiled with -mixedansiports and xsim needs --relax.
* Merge pull request #537 from mithro/yosys-vprClifford Wolf2018-05-044-11/+48
|\ | | | | Improving Yosys when used with VPR
| * Improving vpr output support.Tim 'mithro' Ansell2018-04-184-7/+40
| | | | | | | | | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`.
| * synth_ice40: Rework the vpr blif output slightly.Tim 'mithro' Ansell2018-04-181-4/+8
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* | Add "synth_intel --noiopads"Clifford Wolf2018-04-301-2/+11
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "synth_ice40 -nodffe"Clifford Wolf2018-04-161-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal ↵c60k282018-03-3111-178/+233
| | | | value for the POWER_UP parameter. Fixed and tested Cyclone V device
* coolrunner2: Add an ANDTERM/XOR between chained FFsRobert Ou2018-03-311-0/+58
| | | | | | | In some cases (e.g. the low bits of counters) the design might end up with a flip-flop whose input is directly driven by another flip-flop. This isn't possible in the Coolrunner-II architecture, so add a single AND term and XOR in this case.
* coolrunner2: Split multi-bit netsRobert Ou2018-03-311-0/+1
| | | | | The PAR tool doesn't expect any "dangling" nets with no drivers nor sinks. By splitting the nets, clean removes them.
* coolrunner2: Add extraction for TFFsRobert Ou2018-03-313-0/+54
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* Squelch trailing whitespace, including meta-whitespaceLarry Doolittle2018-03-114-16/+16
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* Add Xilinx RAM64X1D and RAM128X1D simulation modelsClifford Wolf2018-03-074-23/+30
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