| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add _nowide variants of LUT libraries in -nowidelut flows | Eddie Hung | 2019-06-26 | 4 | -13/+44 |
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| * | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-06-26 | 1 | -2/+10 |
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| | * | abc9: Add wire delays to synth_ice40 | David Shah | 2019-06-26 | 1 | -2/+10 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | Merge branch 'koriakin/xc7nocarrymux' into xaig | Eddie Hung | 2019-06-26 | 2 | -9/+26 |
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| | * | synth_ecp5 rename -nomux to -nowidelut, but preserve former | Eddie Hung | 2019-06-26 | 1 | -6/+6 |
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| | * | Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into ↵ | Eddie Hung | 2019-06-26 | 1 | -4/+24 |
| | |\ | | | | | | | | | | koriakin/xc7nocarrymux | ||||
| | | * | synth_xilinx: Add -nocarry and -nomux options. | Marcin Kościelnicki | 2019-04-30 | 1 | -7/+26 |
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| * | | | Realistic delays for RAM32X1D too | Eddie Hung | 2019-06-25 | 1 | -2/+2 |
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| * | | | Add RAM32X1D box info | Eddie Hung | 2019-06-25 | 2 | -4/+12 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-25 | 5 | -8/+72 |
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| | * | | Add RAM32X1D support | Eddie Hung | 2019-06-24 | 5 | -20/+73 |
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| * | | | Use LUT delays for dist RAM delays | Eddie Hung | 2019-06-24 | 1 | -4/+4 |
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| * | | | Re-enable dist RAM boxes for ECP5 | Eddie Hung | 2019-06-24 | 1 | -1/+1 |
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| * | | | Revert "Re-enable dist RAM boxes for ECP5" | Eddie Hung | 2019-06-24 | 1 | -1/+1 |
| | | | | | | | | | | | | | This reverts commit ca0225fcfaa8c9c68647034351a1569464959edf. | ||||
| * | | | Re-enable dist RAM boxes for ECP5 | Eddie Hung | 2019-06-24 | 1 | -1/+1 |
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| * | | | Add Xilinx dist RAM as comb boxes | Eddie Hung | 2019-06-24 | 2 | -0/+16 |
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| * | | | Add comments to ecp5 box | Eddie Hung | 2019-06-22 | 1 | -0/+6 |
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| * | | | Add comment to xc7 box | Eddie Hung | 2019-06-22 | 1 | -0/+3 |
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| * | | | Fix and cleanup ice40 boxes for carry in/out | Eddie Hung | 2019-06-22 | 4 | -313/+25 |
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| * | | | Carry in/out box ordering now move to end, not swap with end | Eddie Hung | 2019-06-22 | 1 | -12/+12 |
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| * | | | Remove DFF and RAMD box info for now | Eddie Hung | 2019-06-21 | 2 | -36/+0 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-21 | 1 | -4/+5 |
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| | * | | ecp5: Improve mapping of $alu when BI is used | David Shah | 2019-06-21 | 1 | -4/+5 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-20 | 1 | -1/+1 |
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| | * | | Fixed small typo in ice40_unlut help summary | acw1251 | 2019-06-19 | 1 | -1/+1 |
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| | * | | Fixed the help summary line for a few commands | acw1251 | 2019-06-19 | 1 | -1/+1 |
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| * | | | Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc | Eddie Hung | 2019-06-20 | 1 | -0/+1 |
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| * | | | Really permute Xilinx LUT mappings as default LUT6.I5:A6 | Eddie Hung | 2019-06-18 | 1 | -16/+16 |
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| * | | | Revert "Fix (do not) permute LUT inputs, but permute mux selects" | Eddie Hung | 2019-06-18 | 1 | -33/+31 |
| | | | | | | | | | | | | | This reverts commit da3d2eedd2b6391621e81b3eaaa28a571e058f9d. | ||||
| * | | | Clean up | Eddie Hung | 2019-06-18 | 1 | -6/+4 |
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| * | | | Fix (do not) permute LUT inputs, but permute mux selects | Eddie Hung | 2019-06-18 | 1 | -31/+33 |
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| * | | | Fix copy-pasta issue | Eddie Hung | 2019-06-17 | 1 | -9/+8 |
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| * | | | Permute INIT for +/xilinx/lut_map.v | Eddie Hung | 2019-06-17 | 1 | -32/+58 |
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| * | | | Simplify comment | Eddie Hung | 2019-06-17 | 1 | -1/+1 |
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| * | | | Update LUT7/8 delays to take account for [ABC]OUTMUX delay | Eddie Hung | 2019-06-17 | 1 | -5/+5 |
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| * | | | Try -W 300 | Eddie Hung | 2019-06-17 | 1 | -1/+2 |
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| * | | | Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O | Eddie Hung | 2019-06-15 | 1 | -2/+2 |
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| * | | | As per @daveshah1 remove async DFF timing from xilinx | Eddie Hung | 2019-06-14 | 1 | -2/+2 |
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| * | | | Resolve comments from @daveshah1 | Eddie Hung | 2019-06-14 | 1 | -1/+1 |
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| * | | | Add XC7_WIRE_DELAY macro to synth_xilinx.cc | Eddie Hung | 2019-06-14 | 1 | -1/+3 |
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| * | | | Update delays based on SymbiFlow/prjxray-db | Eddie Hung | 2019-06-14 | 1 | -12/+13 |
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| * | | | Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut} | Eddie Hung | 2019-06-14 | 4 | -3/+3 |
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| * | | | Comment out dist RAM boxing on ECP5 for now | Eddie Hung | 2019-06-14 | 1 | -1/+1 |
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| * | | | Remove WIP ABC9 flop support | Eddie Hung | 2019-06-14 | 4 | -46/+46 |
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| * | | | Make doc consistent | Eddie Hung | 2019-06-14 | 3 | -3/+6 |
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| * | | | ecp5: Add abc9 option | David Shah | 2019-06-14 | 6 | -70/+184 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | Fix name clash | Eddie Hung | 2019-06-13 | 1 | -4/+8 |
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| * | | | Fix LP SB_LUT4 timing | Eddie Hung | 2019-06-13 | 1 | -1/+1 |
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| * | | | Move neg-pol to pos-pol mapping from ff_map to cells_map.v | Eddie Hung | 2019-06-12 | 1 | -0/+8 |
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| * | | | Reduce diff with master | Eddie Hung | 2019-06-12 | 1 | -1/+1 |
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index : iCE40/yosys | |
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