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| * | | xilinx: cleanup DSP48E1 handling for abc9Eddie Hung2020-03-043-86/+125
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| * | | xilinx: improve specify for DSP48E1Eddie Hung2020-03-041-32/+116
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| * | | xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.vEddie Hung2020-03-042-5/+14
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* | | | Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-032-6/+39
|\ \ \ \ | |/ / / |/| | | Add -flowmap option to `synth{,_ice40}`
| * | | Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-282-6/+39
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* | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-0230-1440/+2803
|\ \ \ \ | | | | | | | | | | abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
| * | | | Remove RAMB{18,36}E1 from cells_xtra.pyEddie Hung2020-02-271-2/+2
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| * | | | xilinx: Update RAMB* specify entriesEddie Hung2020-02-271-11/+42
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| * | | | ice40: add delays to SB_CARRYEddie Hung2020-02-271-0/+30
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| * | | | xilinx: add delays to INVEddie Hung2020-02-271-0/+3
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| * | | | More +/ice40/cells_sim.v fixesEddie Hung2020-02-271-27/+27
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| * | | | Make +/xilinx/cells_sim.v legalEddie Hung2020-02-271-76/+78
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| * | | | Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-273-530/+496
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| * | | | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-7/+10
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| * | | | Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happyEddie Hung2020-02-271-14/+12
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| * | | | ice40: fix specify for inverted clocksEddie Hung2020-02-271-27/+27
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| * | | | Fix tests by gating some specify constructs from iverilogEddie Hung2020-02-271-0/+16
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| * | | | abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-271-2/+6
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| * | | | ice40: specify fixesEddie Hung2020-02-273-66/+66
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| * | | | ice40: move over to specify blocks for -abc9Eddie Hung2020-02-2710-164/+1344
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| * | | | synth_ecp5: use +/abc9_model.vEddie Hung2020-02-271-1/+1
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| * | | | Update xilinx for ABC9Eddie Hung2020-02-273-20/+16
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| * | | | Create +/abc9_model.v for $__ABC9_{DELAY,FF_}Eddie Hung2020-02-272-0/+11
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| * | | | ecp5: remove small LUT entriesEddie Hung2020-02-271-24/+6
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| * | | | Fix commented out specify statementEddie Hung2020-02-271-6/+6
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| * | | | xilinx: improve specify functionalityEddie Hung2020-02-275-446/+519
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| * | | | ecp5: deprecate abc9_{arrival,required} and *.{lut,box}Eddie Hung2020-02-277-86/+120
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| * | | | xilinx: use specify blocks in place of abc9_{arrival,required}Eddie Hung2020-02-271-176/+404
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| * | | | Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-277-426/+151
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| * | | | abc9_ops: -prep_box, to be called onceEddie Hung2020-02-271-1/+1
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| * | | | abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-272-4/+85
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* | | | | coolrunner2: Attempt to give wires/cells more meaningful namesR. Ou2020-03-022-23/+66
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* | | | | coolrunner2: Fix invalid multiple fanouts of XOR/OR gatesR. Ou2020-03-021-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases where multiple output pins share identical combinatorial logic, yosys would only generate one $sop cell and therefore one MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid, so make the fixup pass duplicate cells when necessary. For example, fixes the following code: module top(input a, input b, input clk_, output reg o, output o2); wire clk; BUFG bufg0 ( .I(clk_), .O(clk), ); always @(posedge clk) o = a ^ b; assign o2 = a ^ b; endmodule
* | | | | coolrunner2: Fix packed register+input buffer insertionR. Ou2020-03-021-2/+84
| | | | | | | | | | | | | | | | | | | | | | | | | The register will be packed with the input buffer if and only if the input buffer doesn't have any other loads.
* | | | | coolrunner2: Insert many more required feedthrough cellsR. Ou2020-03-013-102/+215
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* | | | Merge pull request #1709 from rqou/coolrunner2_counterClaire Wolf2020-02-273-0/+165
|\ \ \ \ | | | | | | | | | | Improve CoolRunner-II optimization by using extract_counter pass
| * | | | coolrunner2: Use extract_counter to optimize countersR. Ou2020-02-173-0/+165
| | |/ / | |/| | | | | | | | | | | | | | This tends to make much more efficient pterm usage compared to just throwing the problem at ABC
* | | | Merge pull request #1708 from rqou/coolrunner2-buf-fixClaire Wolf2020-02-274-54/+163
|\ \ \ \ | | | | | | | | | | coolrunner2: Separate and improve buffer cell insertion pass
| * | | | coolrunner2: Separate and improve buffer cell insertion passR. Ou2020-02-164-54/+163
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | The new pass will contain all of the logic for inserting "passthrough" product term and XOR cells as appropriate for the architecture. For example, this commit fixes connecting an input pin directly to another output pin with no logic in between.
* / / / xilinx: mark IOBUFDSE3 IOB pin as externalPiotr Binkowski2020-02-272-1/+2
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* | | Remove executable flag from filesMiodrag Milanovic2020-02-155-0/+0
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* | | abc9: deprecate abc9_ff.init wire for (* abc9_init *) attrEddie Hung2020-02-131-11/+12
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* | | abc9: cleanupEddie Hung2020-02-101-40/+40
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* | Remove unnecessary commaEddie Hung2020-02-071-3/+2
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* | techmap: fix shiftx2mux decompositionEddie Hung2020-02-071-8/+6
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* | xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-074-27/+22
| | | | | | | | | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549
* | xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-073-53/+152
| | | | | | | | | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
* | Merge pull request #1685 from dh73/gowinEddie Hung2020-02-061-1/+1
|\ \ | | | | | | Removing cells_sim from GoWin bram techmap
| * | Removing cells_sim.v from bram techmap passDiego H2020-02-061-1/+1
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* | xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.Marcin Kościelnicki2020-02-0711-1/+370
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