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* DFFINIT is now correctly called for all kinds of flipflop, not just DFFAndrew Zonenberg2016-03-311-0/+6
* Fixed incorrect port name in cells_map.vAndrew Zonenberg2016-03-311-2/+2
* Fixed typo (wasn't written in 2012)Andrew Zonenberg2016-03-301-1/+1
* Fixed typo in greenpak4_counters.ccClifford Wolf2016-03-311-1/+1
* Renamed counters pass to greenpak4_countersAndrew Zonenberg2016-03-303-1/+290
* Added initial implementation of "counters" pass to synth_greenpak4. Can only ...Andrew Zonenberg2016-03-301-0/+2
* Updated tech lib for greenpak4 counter with some clarificationsAndrew Zonenberg2016-03-301-3/+3
* Initial work on greenpak4 counter extraction. Doesn't work but a decent startAndrew Zonenberg2016-03-301-0/+27
* Added splitnets to synth_greenpak4Andrew Zonenberg2016-03-291-0/+2
* Added more cell help messagesClifford Wolf2016-03-291-0/+73
* Fixed indenting in techlibs/greenpak4/gp_dff.libClifford Wolf2016-03-291-5/+5
* Added keep constraint to GP_SYSRESET cellAndrew Zonenberg2016-03-281-0/+2
* Added GP_SYSRESET blockAndrew Zonenberg2016-03-281-0/+7
* Added GP_COUNT8/GP_COUNT14 cellsAndrew Zonenberg2016-03-261-0/+22
* Changed GP_LFOSC parameter configurationAndrew Zonenberg2016-03-261-1/+3
* Added GP_LFOSC cellAndrew Zonenberg2016-03-261-0/+17
* Renamed GP4_V* cells to GP_V* for consistencyAndrew Zonenberg2016-03-261-2/+3
* Added GP_DFFS, GP_DFFR, and GP_DFFSRClifford Wolf2016-03-234-21/+76
* Added GP_DFF INIT parameterClifford Wolf2016-03-232-0/+4
* Improvements in synth_greenpak4, added -part optionClifford Wolf2016-03-211-30/+25
* Added black box modules for all the 7-series design elements (as listed in ug...Clifford Wolf2016-03-194-0/+3441
* Run dffsr2dff in synth_xilinxClifford Wolf2016-02-131-0/+2
* Work around DDR dout sim glitches in ice40 SB_IO sim modelClifford Wolf2016-02-071-1/+7
* Added dffsr2dffClifford Wolf2016-02-021-0/+2
* Progress in cell library documentationClifford Wolf2016-02-011-0/+238
* Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-011-2/+2
* Re-run ice40_opt in "synth_ice40 -abc2"Clifford Wolf2015-12-221-1/+4
* Improvements in ice40_optClifford Wolf2015-12-221-5/+16
* Bugfix in ice40_ffinitClifford Wolf2015-12-221-2/+2
* Improved ice40_ffinitClifford Wolf2015-12-221-1/+22
* Run opt_const before check in default scriptsClifford Wolf2015-12-222-0/+4
* Added "synth_ice40 -abc2"Clifford Wolf2015-12-081-0/+11
* Merge pull request #108 from cseed/masterClifford Wolf2015-12-071-1/+3
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| * Added LO to ICESTORM_LC for LUT cascade route.Cotton Seed2015-12-061-1/+3
* | Added ice40_ffinit passClifford Wolf2015-11-263-0/+145
* | Fixed WE/RE usage in iCE40 BRAM mappingClifford Wolf2015-11-241-8/+8
* | Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handlingClifford Wolf2015-11-061-2/+2
* | Bugfix in Xilinx LUT mappingClifford Wolf2015-10-301-1/+1
* | Progress on cell help messagesClifford Wolf2015-10-201-18/+114
* | Progress on cell help messagesClifford Wolf2015-10-172-53/+106
* | Added "prep" commandClifford Wolf2015-10-142-0/+157
* | Added more cell descriptionsClifford Wolf2015-10-141-0/+85
* | Added first help messages for cell typesClifford Wolf2015-10-144-0/+292
* | Added examples/ top-level directoryClifford Wolf2015-10-1314-279/+0
* | Added read-enable to memory modelClifford Wolf2015-09-256-29/+36
* | Added nlutmapClifford Wolf2015-09-181-2/+2
* | Renamed GreenPAK4 cells, improved GP4 DFF mappingClifford Wolf2015-09-185-9/+50
* | Fixed copy&paste typo in synth_greenpak4Clifford Wolf2015-09-161-3/+3
* | Added GreenPAK4 skeletonClifford Wolf2015-09-164-0/+297
* | Fixed ice40 handling of negclk RAM40Clifford Wolf2015-09-102-12/+12
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