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author | Clifford Wolf <clifford@clifford.at> | 2016-03-23 08:46:10 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-03-23 08:46:10 +0100 |
commit | b4bf787f1091c79d6fed6ac1ec91ebadbceb8023 (patch) | |
tree | 2f4741bce741608d8f58f84b730f9173c1cab571 /techlibs | |
parent | 456c10f16e5b535fc5aa95eacfabbe018fef2348 (diff) | |
download | yosys-b4bf787f1091c79d6fed6ac1ec91ebadbceb8023.tar.gz yosys-b4bf787f1091c79d6fed6ac1ec91ebadbceb8023.tar.bz2 yosys-b4bf787f1091c79d6fed6ac1ec91ebadbceb8023.zip |
Added GP_DFFS, GP_DFFR, and GP_DFFSR
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/greenpak4/cells_map.v | 26 | ||||
-rw-r--r-- | techlibs/greenpak4/cells_sim.v | 47 | ||||
-rw-r--r-- | techlibs/greenpak4/gp_dff.lib | 22 | ||||
-rw-r--r-- | techlibs/greenpak4/synth_greenpak4.cc | 2 |
4 files changed, 76 insertions, 21 deletions
diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v index 667d853da..e24d24973 100644 --- a/techlibs/greenpak4/cells_map.v +++ b/techlibs/greenpak4/cells_map.v @@ -1,20 +1,26 @@ -module \$_DFF_P_ (input D, C, output Q); - GP_DFF _TECHMAP_REPLACE_ ( +module GP_DFFS(input D, CLK, nSET, output reg Q); + parameter [0:0] INIT = 1'bx; + GP_DFFSR #( + .INIT(INIT), + .SRMODE(1'b1), + ) _TECHMAP_REPLACE_ ( .D(D), - .Q(Q), .CLK(C), - .nRSTZ(1'b1), - .nSETZ(1'b1) + .nSR(nSET), + .Q(Q) ); endmodule -module \$_DFFSR_PNN_ (input C, S, R, D, output Q); - GP_DFF _TECHMAP_REPLACE_ ( +module GP_DFFR(input D, CLK, nRST, output reg Q); + parameter [0:0] INIT = 1'bx; + GP_DFFSR #( + .INIT(INIT), + .SRMODE(1'b0), + ) _TECHMAP_REPLACE_ ( .D(D), - .Q(Q), .CLK(C), - .nRSTZ(R), - .nSETZ(S) + .nSR(nRST), + .Q(Q) ); endmodule diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index f8593b9fb..4602c6cc4 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -1,16 +1,45 @@ -module GP_DFF(input D, CLK, nRSTZ, nSETZ, output reg Q); +module GP_DFF(input D, CLK, output reg Q); parameter [0:0] INIT = 1'bx; initial Q = INIT; - always @(posedge CLK, negedge nRSTZ, negedge nSETZ) begin - if (!nRSTZ) - Q <= 1'b0; - else if (!nSETZ) + always @(posedge CLK) begin + Q <= D; + end +endmodule + +module GP_DFFS(input D, CLK, nSET, output reg Q); + parameter [0:0] INIT = 1'bx; + initial Q = INIT; + always @(posedge CLK, negedge nSET) begin + if (!nSET) Q <= 1'b1; else Q <= D; end endmodule +module GP_DFFR(input D, CLK, nRST, output reg Q); + parameter [0:0] INIT = 1'bx; + initial Q = INIT; + always @(posedge CLK, negedge nRST) begin + if (!nRST) + Q <= 1'b0; + else + Q <= D; + end +endmodule + +module GP_DFFSR(input D, CLK, nSR, output reg Q); + parameter [0:0] INIT = 1'bx; + parameter [0:0] SRMODE = 1'bx; + initial Q = INIT; + always @(posedge CLK, negedge nSR) begin + if (!nSR) + Q <= SRMODE; + else + Q <= D; + end +endmodule + module GP_2LUT(input IN0, IN1, output OUT); parameter [3:0] INIT = 0; assign OUT = INIT[{IN1, IN0}]; @@ -25,3 +54,11 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT); parameter [15:0] INIT = 0; assign OUT = INIT[{IN3, IN2, IN1, IN0}]; endmodule + +module GP4_VDD(output OUT); + assign OUT = 1; +endmodule + +module GP4_VSS(output OUT); + assign OUT = 0; +endmodule diff --git a/techlibs/greenpak4/gp_dff.lib b/techlibs/greenpak4/gp_dff.lib index 9e2e46cb4..bc41d18ef 100644 --- a/techlibs/greenpak4/gp_dff.lib +++ b/techlibs/greenpak4/gp_dff.lib @@ -1,5 +1,5 @@ library(gp_dff) { - cell(GP_DFF_NOSR) { + cell(GP_DFF) { area: 1; ff("IQ", "IQN") { clocked_on: CLK; next_state: D; } @@ -9,18 +9,28 @@ library(gp_dff) { pin(Q) { direction: output; function: "IQ"; } } - cell(GP_DFF_SR) { + cell(GP_DFFS) { area: 1; ff("IQ", "IQN") { clocked_on: CLK; next_state: D; - preset: "nSETZ'"; - clear: "nRSTZ'"; } + preset: "nSET'"; } pin(CLK) { direction: input; clock: true; } pin(D) { direction: input; } pin(Q) { direction: output; function: "IQ"; } - pin(nRSTZ) { direction: input; } - pin(nSETZ) { direction: input; } + pin(nSET) { direction: input; } + } + cell(GP_DFFR) { + area: 1; + ff("IQ", "IQN") { clocked_on: CLK; + next_state: D; + clear: "nRST'"; } + pin(CLK) { direction: input; + clock: true; } + pin(D) { direction: input; } + pin(Q) { direction: output; + function: "IQ"; } + pin(nRST) { direction: input; } } } diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index 7d43cf579..04166d8be 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -97,6 +97,7 @@ struct SynthGreenPAK4Pass : public Pass { log(" clean\n"); log("\n"); log(" map_cells:\n"); + log(" dfflibmap -liberty +/greenpak4/gp_dff.lib\n"); log(" techmap -map +/greenpak4/cells_map.v\n"); log(" dffinit -ff GP_DFF Q INIT\n"); log(" clean\n"); @@ -205,6 +206,7 @@ struct SynthGreenPAK4Pass : public Pass { if (check_label(active, run_from, run_to, "map_cells")) { + Pass::call(design, "dfflibmap -liberty +/greenpak4/gp_dff.lib"); Pass::call(design, "techmap -map +/greenpak4/cells_map.v"); Pass::call(design, "dffinit -ff GP_DFF Q INIT"); Pass::call(design, "clean"); |