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| * | | xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-042-9/+16
| * | | xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-043-624/+831
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| * | Merge pull request #1524 from pepijndevos/gowindffinitClifford Wolf2019-12-032-112/+270
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| | * | Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-031-1/+1
| | * | attempt to fix formattingPepijn de Vos2019-11-251-154/+154
| | * | gowin: add and test dff init valuesPepijn de Vos2019-11-252-41/+199
| * | | xilinx: Add missing blackbox cell for BUFPLL.Marcin Kościelnicki2019-11-292-0/+21
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* | | Remove creation of $abc9_control_wireEddie Hung2019-12-061-16/+6
* | | abc9 to use mergeability class to differentiate sync/asyncEddie Hung2019-12-061-12/+15
* | | Remove clkpartEddie Hung2019-12-051-4/+0
* | | Revert "Special abc9_clock wire to contain only clock signal"Eddie Hung2019-12-051-10/+12
* | | Missing wire declarationEddie Hung2019-12-041-0/+1
* | | abc9_map.v to transform INIT=1 to INIT=0Eddie Hung2019-12-041-118/+201
* | | Oh deary meEddie Hung2019-12-041-4/+4
* | | output reg Q -> output Q to suppress warningEddie Hung2019-12-041-8/+8
* | | abc9_map.v to do `zinit' and make INIT = 1'b0Eddie Hung2019-12-041-70/+112
* | | Add abc9_init wire, attach to abc9_flop cellEddie Hung2019-12-031-2/+12
* | | Revert "Add INIT value to abc9_control"Eddie Hung2019-12-031-8/+8
* | | techmap abc_unmap.v before xilinx_srl -fixedEddie Hung2019-12-031-6/+5
* | | Add INIT value to abc9_controlEddie Hung2019-12-021-8/+8
* | | clkpart -unpart into 'finalize'Eddie Hung2019-11-281-3/+4
* | | ean call after abc{,9}Eddie Hung2019-11-271-1/+2
* | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dffEddie Hung2019-11-273-25/+30
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| * | xilinx: Add simulation models for IOBUF and OBUFT.Marcin Kościelnicki2019-11-263-25/+30
* | | Move 'clean' from map_luts to finalizeEddie Hung2019-11-261-1/+1
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-253-5/+11
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| * | clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-1/+5
| * | xilinx: Use INV instead of LUT1 when applicableMarcin Kościelnicki2019-11-251-2/+6
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| * coolrunner2: remove spurious log_pop() call, fixes #1463Martin Pietryka2019-11-231-2/+0
* | Special abc9_clock wire to contain only clock signalEddie Hung2019-11-251-12/+10
* | For abc9, run clkpart before ff_map and after abc9Eddie Hung2019-11-231-0/+2
* | Merge branch 'eddie/clkpart' into xaig_dffEddie Hung2019-11-221-0/+2
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| * gowin: Add missing .gitignore entriesMarcin Kościelnicki2019-11-221-0/+2
* | Merge branch 'eddie/xaig_dff_adff' into xaig_dffEddie Hung2019-11-211-12/+16
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| * | Do not drop async control signals in abc_map.vEddie Hung2019-11-191-12/+16
* | | Add blackbox model for $__ABC9_FF_ so that clock partitioning worksEddie Hung2019-11-201-0/+3
* | | Fix INIT valuesEddie Hung2019-11-201-4/+4
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-1941-23094/+31993
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| * Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-198-43/+547
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| | * Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
| | * add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
| | * Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-164-15/+439
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| | * | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-4/+4
| | * | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1122-22988/+30572
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| | * | | fix wide lutsPepijn de Vos2019-11-061-12/+12
| | * | | add IOBUFPepijn de Vos2019-10-282-1/+10
| | * | | add tristate buffer and testPepijn de Vos2019-10-282-2/+8
| | * | | More formattingPepijn de Vos2019-10-281-55/+49
| | * | | really really fix formatting maybePepijn de Vos2019-10-281-41/+41
| | * | | undo formatting fuckupPepijn de Vos2019-10-281-25/+25
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