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* xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-237-416/+1062
| | | | Signed-off-by: David Shah <dave@ds0.me>
* xilinx: Support multiplier mapping for all families.Marcin Kościelnicki2019-10-229-9/+269
| | | | | This supports several older families that are not yet supported for actual logic synthesis — the intention is to add them soon.
* Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-222-0/+2
|\ | | | | Call memory_dff before DSP mapping to reserve registers (fixes #1447)
| * Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-172-0/+2
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* | ecp5: Pass -nomfs to abc9David Shah2019-10-201-2/+2
| | | | | | | | | | | | Fixes #1459 Signed-off-by: David Shah <dave@ds0.me>
* | Makefile: don't assume python is called `python3`Sean Cross2019-10-194-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io>
* | Merge branch 'master' into mmicko/efinixMiodrag Milanović2019-10-1837-474/+305
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| * ecp5: Add ECLKBRIDGECS blackboxDavid Shah2019-10-111-0/+7
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Add attrmvcp to copy syn_useioff to driving FFDavid Shah2019-10-101-0/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Set syn_useioff on IO FFs to enable packingDavid Shah2019-10-101-8/+8
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * xilinx: Add simulation model for IBUFG.Marcin Kościelnicki2019-10-105-33/+14
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| * Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-0831-228/+236
| |\ | | | | | | Rename abc_* names/attributes to more precisely be abc9_*
| | * Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-044-181/+9
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| | * | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0431-227/+235
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| * | | Add comment on why partial multipliers are 18x18Eddie Hung2019-10-041-4/+8
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| * | | Fix typo in check_label()Eddie Hung2019-10-041-1/+1
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| * | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-2/+6
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| * | Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-043-178/+2
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| * Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-045-31/+4
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| * OopsEddie Hung2019-10-041-1/+1
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| * Ohmilord this wasn't added all this time!?!Eddie Hung2019-10-041-0/+29
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* | FF should be initialized to 0Miodrag Milanovic2019-10-041-1/+3
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* | Add missing latch mappingMiodrag Milanovic2019-10-041-0/+12
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* ecp5: Fix shuffle_enable portDavid Shah2019-10-011-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for mapping 36-bit wide PDP BRAMsDavid Shah2019-10-016-1/+183
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-306-122/+46
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* synth_xilinx: Support latches, remove used-up FF init values.Marcin Kościelnicki2019-09-302-2/+76
| | | | Fixes #1387.
* Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2919-31/+3395
|\ | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5)
| * Re-orderEddie Hung2019-09-272-2/+2
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| * Missing (* mul2dsp *) for sliceBEddie Hung2019-09-271-2/+2
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| * Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run onceEddie Hung2019-09-261-9/+4
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| * TypoEddie Hung2019-09-261-1/+1
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| * select onceEddie Hung2019-09-262-8/+12
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| * Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-263-38/+14
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| * mul2dsp.v slice namesEddie Hung2019-09-251-5/+5
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| * Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicitEddie Hung2019-09-251-3/+1
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| * Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"Eddie Hung2019-09-251-2/+6
| | | | | | | | This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1.
| * Revert "No need for $__mul anymore?"Eddie Hung2019-09-251-8/+8
| | | | | | | | This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827.
| * Only wreduce on t:$addEddie Hung2019-09-251-1/+1
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| * Remove _TECHMAP_CELLTYPE_ check since all $mulEddie Hung2019-09-251-6/+2
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| * No need for $__mul anymore?Eddie Hung2019-09-251-8/+8
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| * Call 'wreduce' after mul2dsp to avoid unextend()Eddie Hung2019-09-251-0/+1
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| * Oops. Actually use __NAME__ in ABC_DSP48E1 macroEddie Hung2019-09-251-1/+1
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| * Add (* techmap_autopurge *) to abc_unmap.v tooEddie Hung2019-09-231-11/+11
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| * Add techmap_autopurge to outputs in abc_map.v tooEddie Hung2019-09-231-11/+11
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| * Revert "Add a xilinx_finalise pass"Eddie Hung2019-09-233-87/+0
| | | | | | | | This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405.
| * Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"Eddie Hung2019-09-231-38/+38
| | | | | | | | This reverts commit 67c2db3486a7b2ff34f89dc861fb66d51ba6101b.
| * Revert "Vivado does not like zero width port connections"Eddie Hung2019-09-231-2/+2
| | | | | | | | This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98.
| * Vivado does not like zero width port connectionsEddie Hung2019-09-231-2/+2
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| * Remove (* techmap_autopurge *) from abc_unmap.v since no effectEddie Hung2019-09-231-38/+38
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