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* Merge pull request #1794 from YosysHQ/dave/mince-abc9-fixDavid Shah2020-03-211-0/+1
|\ | | | | ice40: Map unmapped 'mince' DFFs to gate level
| * ice40: Map unmapped 'mince' DFFs to gate levelDavid Shah2020-03-201-0/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ice40: Fix typos in SPRAM ABC9 timing specsSylvain Munaut2020-03-201-2/+2
|/ | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* xilinx: Mark IOBUFDS.IOB as external padMarcin Kościelnicki2020-03-202-1/+2
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* ice40: Fix SPRAM model to keep data stable if chipselect is lowSylvain Munaut2020-03-141-5/+8
| | | | | | | | According to the official simulation model, and also cross-checked on real hardware, the data output of the SPRAM when chipselect is low is kept stable. It doesn't go undefined. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Fix invalid verilog syntaxMiodrag Milanovic2020-03-141-1/+1
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* Merge pull request #1716 from zeldin/ecp5_fixN. Engelhardt2020-03-091-2/+0
|\ | | | | ecp5: remove unused parameter from \$__ECP5_PDPW16KD
| * remove unused parametersN. Engelhardt2020-03-061-3/+0
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| * ecp5: Add missing parameter to \$__ECP5_PDPW16KDMarcus Comstedt2020-02-221-0/+1
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* | ice40: fix specify for ICE40_{LP,U}Eddie Hung2020-03-051-4/+4
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* | ice40: fix implicit signal in specify, also clamp negative times to 0Eddie Hung2020-03-041-22/+22
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* | Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1Eddie Hung2020-03-044-109/+244
|\ \ | | | | | | xilinx: cleanup DSP48E1 handling for abc9
| * | xilinx: consider DSP48E1.ADREGEddie Hung2020-03-044-5/+8
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| * | xilinx: cleanup DSP48E1 handling for abc9Eddie Hung2020-03-043-86/+125
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| * | xilinx: improve specify for DSP48E1Eddie Hung2020-03-041-32/+116
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| * | xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.vEddie Hung2020-03-042-5/+14
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* | | Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-032-6/+39
|\ \ \ | |/ / |/| | Add -flowmap option to `synth{,_ice40}`
| * | Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-282-6/+39
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* | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-0230-1440/+2803
|\ \ \ | | | | | | | | abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
| * | | Remove RAMB{18,36}E1 from cells_xtra.pyEddie Hung2020-02-271-2/+2
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| * | | xilinx: Update RAMB* specify entriesEddie Hung2020-02-271-11/+42
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| * | | ice40: add delays to SB_CARRYEddie Hung2020-02-271-0/+30
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| * | | xilinx: add delays to INVEddie Hung2020-02-271-0/+3
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| * | | More +/ice40/cells_sim.v fixesEddie Hung2020-02-271-27/+27
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| * | | Make +/xilinx/cells_sim.v legalEddie Hung2020-02-271-76/+78
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| * | | Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-273-530/+496
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| * | | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-7/+10
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| * | | Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happyEddie Hung2020-02-271-14/+12
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| * | | ice40: fix specify for inverted clocksEddie Hung2020-02-271-27/+27
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| * | | Fix tests by gating some specify constructs from iverilogEddie Hung2020-02-271-0/+16
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| * | | abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-271-2/+6
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| * | | ice40: specify fixesEddie Hung2020-02-273-66/+66
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| * | | ice40: move over to specify blocks for -abc9Eddie Hung2020-02-2710-164/+1344
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| * | | synth_ecp5: use +/abc9_model.vEddie Hung2020-02-271-1/+1
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| * | | Update xilinx for ABC9Eddie Hung2020-02-273-20/+16
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| * | | Create +/abc9_model.v for $__ABC9_{DELAY,FF_}Eddie Hung2020-02-272-0/+11
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| * | | ecp5: remove small LUT entriesEddie Hung2020-02-271-24/+6
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| * | | Fix commented out specify statementEddie Hung2020-02-271-6/+6
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| * | | xilinx: improve specify functionalityEddie Hung2020-02-275-446/+519
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| * | | ecp5: deprecate abc9_{arrival,required} and *.{lut,box}Eddie Hung2020-02-277-86/+120
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| * | | xilinx: use specify blocks in place of abc9_{arrival,required}Eddie Hung2020-02-271-176/+404
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| * | | Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-277-426/+151
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| * | | abc9_ops: -prep_box, to be called onceEddie Hung2020-02-271-1/+1
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| * | | abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-272-4/+85
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* | | | coolrunner2: Attempt to give wires/cells more meaningful namesR. Ou2020-03-022-23/+66
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* | | | coolrunner2: Fix invalid multiple fanouts of XOR/OR gatesR. Ou2020-03-021-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases where multiple output pins share identical combinatorial logic, yosys would only generate one $sop cell and therefore one MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid, so make the fixup pass duplicate cells when necessary. For example, fixes the following code: module top(input a, input b, input clk_, output reg o, output o2); wire clk; BUFG bufg0 ( .I(clk_), .O(clk), ); always @(posedge clk) o = a ^ b; assign o2 = a ^ b; endmodule
* | | | coolrunner2: Fix packed register+input buffer insertionR. Ou2020-03-021-2/+84
| | | | | | | | | | | | | | | | | | | | The register will be packed with the input buffer if and only if the input buffer doesn't have any other loads.
* | | | coolrunner2: Insert many more required feedthrough cellsR. Ou2020-03-013-102/+215
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* | | Merge pull request #1709 from rqou/coolrunner2_counterClaire Wolf2020-02-273-0/+165
|\ \ \ | | | | | | | | Improve CoolRunner-II optimization by using extract_counter pass
| * | | coolrunner2: Use extract_counter to optimize countersR. Ou2020-02-173-0/+165
| | |/ | |/| | | | | | | | | | This tends to make much more efficient pterm usage compared to just throwing the problem at ABC
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