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| * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-229-12/+12
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| * | Added GP_VREF cellAndrew Zonenberg2016-04-201-0/+6
* | | Added "shregmap" to synth_greenpak4Clifford Wolf2016-04-231-0/+1
* | | Converted synth_greenpak4 to ScriptPassClifford Wolf2016-04-232-111/+71
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* | Added "yosys -D" featureClifford Wolf2016-04-219-12/+12
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* Added GP_SHREG cellAndrew Zonenberg2016-04-131-0/+23
* Refactoring: alphabetized cells_simAndrew Zonenberg2016-04-131-120/+119
* Fixed missing semicolonAndrew Zonenberg2016-04-091-1/+1
* Added GP_RCOSC cellAndrew Zonenberg2016-04-091-0/+38
* Fixed assertion failure for non-inferrable counters in some casesAndrew Zonenberg2016-04-061-2/+6
* Added second divider to GP_RINGOSCAndrew Zonenberg2016-04-061-8/+13
* Added GP_RINGOSC primitiveAndrew Zonenberg2016-04-061-0/+26
* Added GP_PORAndrew Zonenberg2016-04-041-0/+22
* Added GP_BANDGAP cellAndrew Zonenberg2016-04-041-0/+9
* Removed more debug printsAndrew Zonenberg2016-04-011-1/+0
* Removed forgotten debug codeAndrew Zonenberg2016-04-011-7/+1
* Added GreenPak inverter supportAndrew Zonenberg2016-04-013-4/+13
* Added support for inferring counters with asynchronous resets. Fixed use-afte...Andrew Zonenberg2016-04-011-51/+210
* Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-015-225/+153
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| * Added ScriptPass helper class for script-like passesClifford Wolf2016-03-312-215/+143
| * Renamed opt_share to opt_mergeClifford Wolf2016-03-311-2/+2
| * Renamed opt_const to opt_exprClifford Wolf2016-03-315-12/+12
* | DFFINIT is now correctly called for all kinds of flipflop, not just DFFAndrew Zonenberg2016-03-311-0/+6
* | Fixed incorrect port name in cells_map.vAndrew Zonenberg2016-03-311-2/+2
* | Fixed typo (wasn't written in 2012)Andrew Zonenberg2016-03-301-1/+1
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* Fixed typo in greenpak4_counters.ccClifford Wolf2016-03-311-1/+1
* Renamed counters pass to greenpak4_countersAndrew Zonenberg2016-03-303-1/+290
* Added initial implementation of "counters" pass to synth_greenpak4. Can only ...Andrew Zonenberg2016-03-301-0/+2
* Updated tech lib for greenpak4 counter with some clarificationsAndrew Zonenberg2016-03-301-3/+3
* Initial work on greenpak4 counter extraction. Doesn't work but a decent startAndrew Zonenberg2016-03-301-0/+27
* Added splitnets to synth_greenpak4Andrew Zonenberg2016-03-291-0/+2
* Added more cell help messagesClifford Wolf2016-03-291-0/+73
* Fixed indenting in techlibs/greenpak4/gp_dff.libClifford Wolf2016-03-291-5/+5
* Added keep constraint to GP_SYSRESET cellAndrew Zonenberg2016-03-281-0/+2
* Added GP_SYSRESET blockAndrew Zonenberg2016-03-281-0/+7
* Added GP_COUNT8/GP_COUNT14 cellsAndrew Zonenberg2016-03-261-0/+22
* Changed GP_LFOSC parameter configurationAndrew Zonenberg2016-03-261-1/+3
* Added GP_LFOSC cellAndrew Zonenberg2016-03-261-0/+17
* Renamed GP4_V* cells to GP_V* for consistencyAndrew Zonenberg2016-03-261-2/+3
* Added GP_DFFS, GP_DFFR, and GP_DFFSRClifford Wolf2016-03-234-21/+76
* Added GP_DFF INIT parameterClifford Wolf2016-03-232-0/+4
* Improvements in synth_greenpak4, added -part optionClifford Wolf2016-03-211-30/+25
* Added black box modules for all the 7-series design elements (as listed in ug...Clifford Wolf2016-03-194-0/+3441
* Run dffsr2dff in synth_xilinxClifford Wolf2016-02-131-0/+2
* Work around DDR dout sim glitches in ice40 SB_IO sim modelClifford Wolf2016-02-071-1/+7
* Added dffsr2dffClifford Wolf2016-02-021-0/+2
* Progress in cell library documentationClifford Wolf2016-02-011-0/+238
* Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-011-2/+2
* Re-run ice40_opt in "synth_ice40 -abc2"Clifford Wolf2015-12-221-1/+4
* Improvements in ice40_optClifford Wolf2015-12-221-5/+16
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