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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-09 01:18:02 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-09 01:18:02 -0700 |
| commit | f1679936fe3f40d7fab3438a00dad2fed5a5f00e (patch) | |
| tree | 6ebf359b2a68792e49ab01b04cf5376945eed277 /techlibs | |
| parent | c1b8d3b580601ad9ba61b247fa967efdfe19fcda (diff) | |
| download | yosys-f1679936fe3f40d7fab3438a00dad2fed5a5f00e.tar.gz yosys-f1679936fe3f40d7fab3438a00dad2fed5a5f00e.tar.bz2 yosys-f1679936fe3f40d7fab3438a00dad2fed5a5f00e.zip | |
Fixed missing semicolon
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 800fe3ab5..7c9af873f 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -124,7 +124,7 @@ module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC) parameter AUTO_PWRDN = 0; parameter PRE_DIV = 1; parameter FABRIC_DIV = 1; - parameter OSC_FREQ = "25k" + parameter OSC_FREQ = "25k"; initial CLKOUT_PREDIV = 0; initial CLKOUT_FABRIC = 0; |