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* Re-arrange FD orderEddie Hung2019-12-313-182/+182
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* Missing characterEddie Hung2019-12-311-1/+1
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* Cleanup xilinx boxesEddie Hung2019-12-312-391/+425
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* Cleanup ice40 boxesEddie Hung2019-12-313-30/+43
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* Cleanup ecp5 boxesEddie Hung2019-12-314-35/+31
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* Update abc9_xc7.box commentsEddie Hung2019-12-311-18/+18
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* FDCE ports to be alphabeticalEddie Hung2019-12-311-3/+3
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* Fix attributes on $__ABC9_ASYNC[01] whiteboxEddie Hung2019-12-311-2/+2
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* Fix incorrect $__ABC9_ASYNC[01] boxEddie Hung2019-12-311-2/+2
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* Do not offset FD* box timings due to -46ps TsuEddie Hung2019-12-301-12/+21
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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-3010-32/+377
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| * Merge pull request #1589 from YosysHQ/iopad_defaultMiodrag Milanović2019-12-301-11/+6
| |\ | | | | | | Make iopad option default for all xilinx flows
| | * Merge remote-tracking branch 'origin/master' into iopad_defaultMiodrag Milanovic2019-12-288-10/+368
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| | * | Addressed review commentsMiodrag Milanovic2019-12-211-2/+3
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| | * | iopad no op for compatibility with old scriptsMiodrag Milanovic2019-12-211-0/+3
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| | * | Make iopad option default for all xilinx flowsMiodrag Milanovic2019-12-211-14/+5
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| * | | Nitpick cleanup for ecp5Eddie Hung2019-12-272-11/+3
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| * | Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgenMarcin Kościelnicki2019-12-253-3/+6
| |\ \ | | | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support.
| | * | xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-223-3/+6
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| * / xilinx: Test our DSP48A/DSP48A1 simulation models.Marcin Kościelnicki2019-12-235-7/+362
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* | Tidy up abc9_map.vEddie Hung2019-12-301-103/+103
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* | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-302-2/+98
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
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| * Add abc9_arrival times for RAM{32,64}MEddie Hung2019-12-201-24/+10
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-204-172/+240
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| * Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-201-0/+78
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| * Revert "Optimise write_xaiger"Eddie Hung2019-12-203-15/+0
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| * Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-193-0/+15
| |\ | | | | | | Optimise write_xaiger
| | * techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-063-0/+15
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| * | xilinx: Add simulation models for remaining CLB primitives.Marcin Kościelnicki2019-12-193-156/+210
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| * | xilinx_dffopt: Keep order of LUT inputs.Marcin Kościelnicki2019-12-191-16/+30
| | | | | | | | | | | | See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
* | | Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-191-0/+78
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* | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-195-36/+55
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1914-81/+995
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| * | Merge pull request #1563 from YosysHQ/dave/async-prldDavid Shah2019-12-182-4/+28
| |\ \ | | | | | | | | ecp5: Add support for mapping PRLD FFs
| | * | ecp5: Add support for mapping PRLD FFsDavid Shah2019-12-072-4/+28
| | |/ | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-186-22/+389
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| * | xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-184-38/+228
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.
| * | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutramEddie Hung2019-12-163-12/+301
| |\ \ | | | | | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M
| | * \ Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into ↵Eddie Hung2019-12-161-2/+8
| | |\ \ | | | | | | | | | | | | | | | eddie/xilinx_lutram
| | | * | Populate DID/DOD even if unusedEddie Hung2019-12-161-2/+8
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| | * | | Rename *RAM{32,64}M rules to RAM{32X2,64X1}QEddie Hung2019-12-162-6/+6
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| | * | Disable RAM16X1D match rule; carry-over from LUT4 archesEddie Hung2019-12-131-6/+9
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| | * | RAM64M8 to also have [5:0] for addressEddie Hung2019-12-131-8/+8
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| | * | Add RAM32X6SDP and RAM64X3SDP modesEddie Hung2019-12-122-8/+120
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| | * | Fix RAM64M model to have 6 bit address busEddie Hung2019-12-121-4/+4
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| | * | Add memory rules for RAM16X1D, RAM32M, RAM64MEddie Hung2019-12-122-0/+168
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| * | | Add unconditional match blocks for force RAMEddie Hung2019-12-161-4/+36
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| * | | Update xc7/xcu bram rulesEddie Hung2019-12-161-8/+4
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| * | | Removing fixed attribute value to !ramstyle rulesDiego H2019-12-151-4/+4
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