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* Map to SB_LUT4 from fastest input firstEddie Hung2019-04-171-7/+11
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* Mark seq output ports with "abc_flop_q" attrEddie Hung2019-04-171-24/+24
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* Also update Makefile.incEddie Hung2019-04-171-3/+3
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* synth_ice40 to use renamed filesEddie Hung2019-04-171-2/+2
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* Rename to abc.*Eddie Hung2019-04-173-0/+0
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* Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"Eddie Hung2019-04-177-102/+35
| | | | This reverts commit a7632ab3326c5247b8152a53808413b259c13253.
* Try using an ICE40_CARRY_LUT primitive to avoid ABC issuesEddie Hung2019-04-177-35/+102
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* Fix spacingEddie Hung2019-04-171-5/+5
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* Add SB_LUT4 to box libraryEddie Hung2019-04-163-0/+16
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* Add ice40 box filesEddie Hung2019-04-166-1/+27
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* Add support for synth_xilinx -abc9 and ignore abc9 -dress optEddie Hung2019-04-121-1/+9
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* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-124-44/+69
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| * Merge pull request #928 from litghost/add_xc7_sim_modelsEddie Hung2019-04-123-41/+60
| |\ | | | | | | Add additional cells sim models for core 7-series primitives.
| | * Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Fixing issues in CycloneV cell simDiego2019-04-111-3/+9
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* | Merge branch 'master' into xaigEddie Hung2019-04-0832-384/+1646
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| * xilinx: Add keep attribute where appropriateDavid Shah2019-03-222-25/+31
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Remove ice40/cells_sim.v hack to avoid warning for blocking memory writesClifford Wolf2019-03-121-19/+0
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix typo in ice40_braminit help msgClifford Wolf2019-03-091-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #859 from smunaut/ice40_braminitClifford Wolf2019-03-094-37/+212
| |\ | | | | | | iCE40 BRAM primitives init from file
| | * ice40: Run ice40_braminit pass by defaultSylvain Munaut2019-03-081-0/+1
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| | * ice40: Add ice40_braminit pass to allow initialization of BRAM from fileSylvain Munaut2019-03-083-37/+211
| | | | | | | | | | | | | | | | | | | | | | | | This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will initialize content from a hex file. Same behavior is imlemented in the simulation model and in a new pass for actual synthesis Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | Add link to SF2 / igloo2 macro library guideClifford Wolf2019-03-071-21/+24
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improvements in sf2 cells_sim.vClifford Wolf2019-03-062-30/+251
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add sf2 techmap rules for more FF typesClifford Wolf2019-03-061-25/+39
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Refactor SF2 iobuf insertion, Add clkint insertionClifford Wolf2019-03-063-83/+152
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improvements in SF2 flow and demoClifford Wolf2019-03-052-8/+23
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-0510-176/+570
| |\ \ | | | | | | | | Changes required for VPR place and route in synth_xilinx
| | * | Revert BRAM WRITE_MODE changes.Keith Rothman2019-03-041-12/+12
| | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * | Revert FF models to include IS_x_INVERTED parameters.Keith Rothman2019-03-011-6/+34
| | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * | Use singular for disabling of DRAM or BRAM inference.Keith Rothman2019-03-011-13/+13
| | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * | Modify arguments to match existing style.Keith Rothman2019-03-011-6/+6
| | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * | Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-0111-221/+587
| | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | | Merge pull request #850 from daveshah1/ecp5_warn_conflictClifford Wolf2019-03-051-2/+7
| |\ \ \ | | | | | | | | | | ecp5: Demote conflicting FF init values to a warning
| | * | | ecp5: Demote conflicting FF init values to a warningDavid Shah2019-03-041-2/+7
| | |/ / | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * / / Use "write_edif -pvector bra" for Xilinx EDIF filesClifford Wolf2019-03-051-1/+1
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Fix ECP5 cells_sim for iverilogMiodrag Milanovic2019-03-011-2/+3
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| * | Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_modeClifford Wolf2019-02-281-2/+2
| |\ \ | | | | | | | | ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
| | * | ice40: use 2 bits for READ/WRITE MODE for SB_RAM mapElms2019-02-281-2/+2
| | |/ | | | | | | | | | | | | | | | EBLIF output .param will only use necessary 2 bits Signed-off-by: Elms <elms@freshred.net>
| * | Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-286-19/+19
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| * | Merge pull request #794 from daveshah1/ecp5improveClifford Wolf2019-02-287-12/+388
| |\ \ | | |/ | |/| ECP5 Improvements
| | * ecp5: Compatibility with Migen AsyncResetSynchronizerDavid Shah2019-02-252-0/+20
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * ecp5: Add DDRDLLADavid Shah2019-02-191-0/+9
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * ecp5: Add DELAYF/DELAYG blackboxesDavid Shah2019-02-191-0/+18
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * ecp5: Add ECLKSYNCB blackboxDavid Shah2019-02-131-1/+7
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * ecp5: Full set of IO-related blackboxesDavid Shah2019-02-121-0/+102
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * ecp5: Support for flipflop initialisationDavid Shah2019-01-223-4/+199
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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