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Author
Age
Files
Lines
*
Call memory_dff before DSP mapping to reserve registers (fixes #1447)
N. Engelhardt
2019-10-17
2
-0
/
+2
*
ecp5: Add ECLKBRIDGECS blackbox
David Shah
2019-10-11
1
-0
/
+7
*
ecp5: Add attrmvcp to copy syn_useioff to driving FF
David Shah
2019-10-10
1
-0
/
+1
*
ecp5: Set syn_useioff on IO FFs to enable packing
David Shah
2019-10-10
1
-8
/
+8
*
xilinx: Add simulation model for IBUFG.
Marcin KoĆcielnicki
2019-10-10
5
-33
/
+14
*
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
Eddie Hung
2019-10-08
31
-228
/
+236
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\
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*
Merge branch 'master' into eddie/abc_to_abc9
Eddie Hung
2019-10-04
4
-181
/
+9
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\
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*
|
Rename abc_* names/attributes to more precisely be abc9_*
Eddie Hung
2019-10-04
31
-227
/
+235
*
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Add comment on why partial multipliers are 18x18
Eddie Hung
2019-10-04
1
-4
/
+8
*
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Fix typo in check_label()
Eddie Hung
2019-10-04
1
-1
/
+1
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/
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/
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*
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Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`
Eddie Hung
2019-10-04
1
-2
/
+6
*
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Remove DSP48E1 from *_cells_xtra.v
Eddie Hung
2019-10-04
3
-178
/
+2
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/
*
Panic over. Model was elsewhere. Re-arrange for consistency
Eddie Hung
2019-10-04
5
-31
/
+4
*
Oops
Eddie Hung
2019-10-04
1
-1
/
+1
*
Ohmilord this wasn't added all this time!?!
Eddie Hung
2019-10-04
1
-0
/
+29
*
ecp5: Fix shuffle_enable port
David Shah
2019-10-01
1
-2
/
+2
*
ecp5: Add support for mapping 36-bit wide PDP BRAMs
David Shah
2019-10-01
6
-1
/
+183
*
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
Eddie Hung
2019-09-30
6
-122
/
+46
*
synth_xilinx: Support latches, remove used-up FF init values.
Marcin KoĆcielnicki
2019-09-30
2
-2
/
+76
*
Merge pull request #1359 from YosysHQ/xc7dsp
Eddie Hung
2019-09-29
19
-31
/
+3395
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\
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*
Re-order
Eddie Hung
2019-09-27
2
-2
/
+2
|
*
Missing (* mul2dsp *) for sliceB
Eddie Hung
2019-09-27
1
-2
/
+2
|
*
Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once
Eddie Hung
2019-09-26
1
-9
/
+4
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*
Typo
Eddie Hung
2019-09-26
1
-1
/
+1
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*
select once
Eddie Hung
2019-09-26
2
-8
/
+12
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*
Stop trying to be too smart by prematurely optimising
Eddie Hung
2019-09-26
3
-38
/
+14
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*
mul2dsp.v slice names
Eddie Hung
2019-09-25
1
-5
/
+5
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*
Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit
Eddie Hung
2019-09-25
1
-3
/
+1
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*
Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"
Eddie Hung
2019-09-25
1
-2
/
+6
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*
Revert "No need for $__mul anymore?"
Eddie Hung
2019-09-25
1
-8
/
+8
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*
Only wreduce on t:$add
Eddie Hung
2019-09-25
1
-1
/
+1
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*
Remove _TECHMAP_CELLTYPE_ check since all $mul
Eddie Hung
2019-09-25
1
-6
/
+2
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*
No need for $__mul anymore?
Eddie Hung
2019-09-25
1
-8
/
+8
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*
Call 'wreduce' after mul2dsp to avoid unextend()
Eddie Hung
2019-09-25
1
-0
/
+1
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*
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
Eddie Hung
2019-09-25
1
-1
/
+1
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*
Add (* techmap_autopurge *) to abc_unmap.v too
Eddie Hung
2019-09-23
1
-11
/
+11
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*
Add techmap_autopurge to outputs in abc_map.v too
Eddie Hung
2019-09-23
1
-11
/
+11
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*
Revert "Add a xilinx_finalise pass"
Eddie Hung
2019-09-23
3
-87
/
+0
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*
Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"
Eddie Hung
2019-09-23
1
-38
/
+38
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*
Revert "Vivado does not like zero width port connections"
Eddie Hung
2019-09-23
1
-2
/
+2
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*
Vivado does not like zero width port connections
Eddie Hung
2019-09-23
1
-2
/
+2
|
*
Remove (* techmap_autopurge *) from abc_unmap.v since no effect
Eddie Hung
2019-09-23
1
-38
/
+38
|
*
Add a xilinx_finalise pass
Eddie Hung
2019-09-23
3
-0
/
+87
|
*
Grammar
Eddie Hung
2019-09-20
1
-1
/
+1
|
*
Fix signedness bug
Eddie Hung
2019-09-20
1
-2
/
+2
|
*
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
Eddie Hung
2019-09-20
2
-3
/
+2
|
*
Revert "Move mul2dsp before wreduce"
Eddie Hung
2019-09-20
1
-4
/
+5
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*
Move mul2dsp before wreduce
Eddie Hung
2019-09-20
1
-5
/
+4
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*
Tidy up, fix undriven
Eddie Hung
2019-09-19
1
-32
/
+34
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*
$__ABC_REG to have WIDTH parameter
Eddie Hung
2019-09-19
2
-17
/
+18
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