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* Merge pull request #2585 from YosysHQ/dave/nexus-dotproductgatecat2021-02-121-0/+115
|\ | | | | nexus: Add MULTADDSUB9X9WIDE sim model
| * nexus: Add MULTADDSUB9X9WIDE sim modelDavid Shah2020-12-081-0/+115
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | verilog: significant block scoping improvementsZachary Snow2021-01-315-81/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* | xilinx_dffopt: Don't crash on missing IS_*_INVERTED.Marcelina Kościelnicka2021-01-271-3/+3
| | | | | | | | | | | | | | | | The presence of IS_*_INVERTED on FD* cells follows Vivado, which apparently has been decided by a dice roll. Just assume false if the parameter doesn't exist. Fixes #2559.
* | xilinx: Add FDRSE_1, FDCPE_1.Marcelina Kościelnicka2021-01-271-0/+80
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* | Fix some trivial typos.Tom Verbeure2021-01-031-5/+5
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* | Merge pull request #2480 from YosysHQ/dave/nexus-lramwhitequark2021-01-015-1/+227
|\| | | | | nexus: Add LRAM inference
| * nexus: Add LRAM inferenceDavid Shah2020-12-075-1/+227
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | xilinx: Add some missing blackbox cells.Marcelina Kościelnicka2020-12-213-798/+6276
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* | xilinx: Regenerate cells_xtra.v using Vivado 2020.2Marcelina Kościelnicka2020-12-212-42/+49
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* | xilinx: Add FDDRCPE and FDDRRSE blackbox cells.Marcelina Kościelnicka2020-12-172-0/+33
|/ | | | | These are necessary primitives for proper DDR support on Virtex 2 and Spartan 3.
* nexus: More efficient CO mappingDavid Shah2020-12-021-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* add -noalu and -json option for apiculaPepijn de Vos2020-11-301-3/+32
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* nexus: DSP inference supportDavid Shah2020-11-203-1/+117
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #2441 from YosysHQ/dave/nexus_dsp_simMiodrag Milanović2020-11-183-250/+573
|\ | | | | nexus: Add DSP simulation model
| * nexus: Add DSP simulation modelDavid Shah2020-11-183-250/+573
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fix duplicated parameter name typoMiodrag Milanovic2020-11-181-1/+1
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* | synth_gowin: Add rPLL blackboxKonrad Beckmann2020-11-111-0/+45
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* nexus: Add make_transp to BRAMsDavid Shah2020-10-221-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #2405 from byuccl/fix_xilinx_cellsclairexen2020-10-201-2/+2
|\ | | | | xilinx/cells_sim.v: Move signal declaration to before first use
| * Move signal declarations to before first useJeff Goeders2020-10-191-2/+2
| | | | | | | | Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
* | synth_nexus: Initial implementationDavid Shah2020-10-1514-0/+12229
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)Eddie Hung2020-09-232-17/+65
| | | | | | | | | | | * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled
* intel_alm: better map wide but shallow multipliesDan Ravensloft2020-08-281-2/+6
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* intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-265-10/+103
| | | | | | Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
* synth_intel: Remove incomplete Arria 10 GX support.Marcelina Kościelnicka2020-08-215-192/+4
| | | | | | The techmap rules for this target do not work in the first place (note lack of >2-input LUT mappings), and if proper support is ever added, it'd be better placed in the synth_intel_alm backend.
* intel: move Cyclone V support to intel_almDan Ravensloft2020-08-207-203/+11
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* Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixesclairexen2020-08-201-67/+35
|\ | | | | techmap/shift_shiftx: Remove the "shiftx2mux" special path.
| * techmap/shift_shiftx: Remove the "shiftx2mux" special path.Marcelina Kościelnicka2020-08-201-67/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Our techmap rules for $shift and $shiftx cells contained a special path that aimed to decompose the shift LSB-first instead of MSB-first in select cases that come up in pmux lowering. This path was needlessly overcomplicated and contained bugs. Instead of doing that, just switch over the main path to iterate LSB-first (except for the specially-handled MSB for signed shifts and overflow handling). This also makes the code consistent with shl/shr/sshl/sshr cells, which are already decomposed LSB-first. Fixes #2346.
* | Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-patternclairexen2020-08-202-4/+4
|\ \ | |/ |/| techmap: Add support for [] wildcards in techmap_celltype.
| * techmap: Add support for [] wildcards in techmap_celltype.Marcelina Kościelnicka2020-08-022-4/+4
| | | | | | | | Fixes #1826.
* | Respect \A_SIGNED for $shiftXiretza2020-08-182-6/+16
| | | | | | | | | | | | This reflects the behaviour of $shr/$shl, which sign-extend their A operands to the size of their output, then do a logical shift (shift in 0-bits).
* | intel_alm: fix typo in MISTRAL_MUL27X27 cell nameDan Ravensloft2020-08-131-1/+1
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* | intel_alm: add more megafunctions. NFC.Dan Ravensloft2020-08-121-0/+431
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* | Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-077-29/+26
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* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-312-2/+2
| | | | | Adds -noclkinv option just in case the old behavior was actually useful to someone.
* synth_ice40: Use opt_dff.Marcelina Kościelnicka2020-07-304-142/+6
| | | | | | | | | The main part is converting ice40_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the mux patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-301-17/+12
| | | | | | | | | The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-277-39/+127
| | | | This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
* intel_alm: increase abc9 -WDan Ravensloft2020-07-261-1/+1
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* Merge pull request #2294 from Ravenslofty/intel_alm_timingsclairexen2020-07-234-72/+91
|\ | | | | intel_alm: add additional ABC9 timings
| * intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-234-72/+91
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* | Remove EXPLICIT_CARRY logic.Keith Rothman2020-07-233-150/+2
|/ | | | | | | The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY within yosys itself. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* sf2: Emit CLKINT even if -clkbuf not passedMarcelina Kościelnicka2020-07-171-2/+6
| | | | This restores pre #2229 behavior.
* Merge pull request #2274 from YosysHQ/mwk/anlogic-ff-fixMiodrag Milanović2020-07-171-12/+12
|\ | | | | anlogic: Fix FF mapping.
| * anlogic: Fix FF mapping.Marcelina Kościelnicka2020-07-171-12/+12
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* | Merge pull request #2229 from Ravenslofty/sf2_remove_sf2_iobsclairexen2020-07-164-214/+135
|\ \ | |/ |/| sf2: replace sf2_iobs with {clkbuf,iopad}map
| * sf2: replace sf2_iobs with {clkbuf,iopad}mapDan Ravensloft2020-07-094-214/+135
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* | Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogicMiodrag Milanović2020-07-163-50/+35
|\ \ | | | | | | anlogic: Use dfflegalize.
| * | anlogic: Use dfflegalize.Marcelina Kościelnicka2020-07-143-50/+35
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