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* Add flooring modulo operatorXiretza2020-05-282-3/+124
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* xilinx: tidy up cells_sim.v a littleEddie Hung2020-05-251-5/+7
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* ecp5: cleanup unused +/ecp5/abc9_model.vEddie Hung2020-05-233-14/+0
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-1939-24/+232
| | | | Fixes #2058.
* abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_Eddie Hung2020-05-142-14/+2
| | | | instead of moving them to $__ prefix
* abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove itEddie Hung2020-05-142-5/+4
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* abc9_ops/xaiger: further reducing Module::derive() calls by ...Eddie Hung2020-05-142-7/+5
| | | | replacing _all_ (* abc9_box *) instantiations with their derived types
* Cleanup; reduce Module::derive() callsEddie Hung2020-05-142-4/+4
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* ecp5: latches_map.v if *not* -asyncprldEddie Hung2020-05-141-2/+2
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* ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.vEddie Hung2020-05-144-43/+3
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* ecp5: fix rebase mistakeEddie Hung2020-05-141-3/+3
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* xilinx: gate specify/attributes from iverilogEddie Hung2020-05-141-1/+3
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* abc9: only do +/abc9_map if `DFFEddie Hung2020-05-141-0/+2
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* ecp5: TRELLIS_FF bypass path only in async modeEddie Hung2020-05-141-8/+8
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* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-143-4/+4
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* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-143-4/+198
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* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-148-763/+129
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-142-10/+26
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* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-144-4/+3
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* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-144-0/+55
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* abc9_ops: -prep_dff_map to error if async flop foundEddie Hung2020-05-141-4/+0
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* Uncomment negative setup times; clamp to zero for connectivityEddie Hung2020-05-141-13/+29
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* Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"Eddie Hung2020-05-143-220/+64
| | | | This reverts commit 8c702b6cc0221a00021a3e4661c883bb591c924b.
* ecp5: (* abc9_flop *) gated behind YOSYSEddie Hung2020-05-141-0/+2
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* ecp5: add synth_ecp5 -dff to work with -abc9Eddie Hung2020-05-142-12/+47
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* ice40: synth_ice40 cleanupEddie Hung2020-05-141-13/+3
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* ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-initEddie Hung2020-05-143-64/+220
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* ice40: add synth_ice40 -dff option, support with -abc9Eddie Hung2020-05-142-8/+41
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* ice40: split out cells_map.v into ff_map.vEddie Hung2020-05-143-31/+29
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* synth_xilinx: rename dff_mode -> dffEddie Hung2020-05-141-8/+10
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* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-145-369/+5
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* Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-142-7/+30
|\ | | | | ast: swap range regardless of range_left >= 0
| * techlibs/common: more robustness when *_WIDTH = 0Eddie Hung2020-05-052-7/+30
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* | ice40: fix ICESTORM_LC process sensitivityEddie Hung2020-05-121-1/+1
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* | ice40: fix whitespaceEddie Hung2020-05-121-15/+14
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* | ecp5: Add missing SERDES parametersDavid Shah2020-05-121-0/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-078-52/+143
| | | | | | | | | | | | | | | | | | | | By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
* | synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-043-11/+34
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* gowin,ecp5: remove generated files in `make clean`.whitequark2020-04-242-2/+10
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* intel_alm: cleanup duplicationDan Ravensloft2020-04-245-113/+64
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* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+10
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* ecp5: ecp5_gsr to skip cells that don't have GSR parameter againEddie Hung2020-04-221-1/+1
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* xilinx: improve xilinx_dffopt messageEddie Hung2020-04-221-3/+6
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* Cleanup use of hard-coded default parameters in light of #1945Eddie Hung2020-04-222-12/+6
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* intel_alm: Documentation improvementsDan Ravensloft2020-04-213-14/+127
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* Use default parameter value in getParamMarcelina Kościelnicka2020-04-211-3/+3
| | | | Fixes #1822.
* ecp5: Force SIGNED ports to be 1 bitDavid Shah2020-04-161-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix the truth table for $_SR_* cells.Marcelina Kościelnicka2020-04-153-26/+21
| | | | | | | | This brings the documented behavior for these cells in line with $_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S. The models were already reflecting that behavior. Also get rid of sim-synth mismatch in the models while we're at it.
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-159-10/+1
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* synth_intel_alm: VQM supportDan Ravensloft2020-04-152-6/+3
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