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* | | synth_gowin: ABC9 supportDan Ravensloft2020-07-052-34/+340
* | | Merge pull request #2236 from YosysHQ/mwk/dfflegalize-ice40Marcelina Kościelnicka2020-07-054-208/+24
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| * | | ice40: Use dfflegalize.Marcelina Kościelnicka2020-07-054-208/+24
* | | | ecp5: Use dfflegalize.Marcelina Kościelnicka2020-07-054-254/+96
* | | | Merge pull request #2232 from YosysHQ/mwk/gowin-sim-initMarcelina Kościelnicka2020-07-051-8/+8
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| * | | | gowin: Fix INIT values in sim library.Marcelina Kościelnicka2020-07-051-8/+8
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* | | | intel_alm: DSP inferenceDan Ravensloft2020-07-056-9/+186
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* | | gowin: replace determine_init with setundefDan Ravensloft2020-07-043-74/+1
* | | synth_intel_alm: Use dfflegalize.Marcelina Kościelnicka2020-07-042-121/+9
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* | Improve MISTRAL_FF specify rulesDan Ravensloft2020-07-041-5/+4
* | intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FFEddie Hung2020-07-042-47/+2
* | intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLYEddie Hung2020-07-044-4/+4
* | intel_alm: ABC9 sequential optimisationsDan Ravensloft2020-07-047-19/+149
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* simcells: Fix reset polarity for $_DLATCH_???_ cells.Marcelina Kościelnicka2020-06-302-5/+5
* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-2316-128/+128
* Add new FF types to simplemap.Marcelina Kościelnicka2020-06-231-1/+1
* Add new builtin FF typesMarcelina Kościelnicka2020-06-233-0/+2293
* Use C++11 final/override keywords.whitequark2020-06-1831-95/+95
* Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTHXark2020-06-141-7/+7
* intel_alm: fix DFFE matchingDan Ravensloft2020-06-111-1/+1
* Do not optimize away FFs in "prep" and Verific fron-endClaire Wolf2020-06-091-2/+2
* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-1/+1
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| * abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_Eddie Hung2020-05-291-1/+1
* | Add flooring division operatorXiretza2020-05-282-0/+71
* | Add flooring modulo operatorXiretza2020-05-282-3/+124
* | xilinx: tidy up cells_sim.v a littleEddie Hung2020-05-251-5/+7
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* ecp5: cleanup unused +/ecp5/abc9_model.vEddie Hung2020-05-233-14/+0
* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-1939-24/+232
* abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_Eddie Hung2020-05-142-14/+2
* abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove itEddie Hung2020-05-142-5/+4
* abc9_ops/xaiger: further reducing Module::derive() calls by ...Eddie Hung2020-05-142-7/+5
* Cleanup; reduce Module::derive() callsEddie Hung2020-05-142-4/+4
* ecp5: latches_map.v if *not* -asyncprldEddie Hung2020-05-141-2/+2
* ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.vEddie Hung2020-05-144-43/+3
* ecp5: fix rebase mistakeEddie Hung2020-05-141-3/+3
* xilinx: gate specify/attributes from iverilogEddie Hung2020-05-141-1/+3
* abc9: only do +/abc9_map if `DFFEddie Hung2020-05-141-0/+2
* ecp5: TRELLIS_FF bypass path only in async modeEddie Hung2020-05-141-8/+8
* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-143-4/+4
* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-143-4/+198
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-148-763/+129
* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-142-10/+26
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-144-4/+3
* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-144-0/+55
* abc9_ops: -prep_dff_map to error if async flop foundEddie Hung2020-05-141-4/+0
* Uncomment negative setup times; clamp to zero for connectivityEddie Hung2020-05-141-13/+29
* Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"Eddie Hung2020-05-143-220/+64
* ecp5: (* abc9_flop *) gated behind YOSYSEddie Hung2020-05-141-0/+2
* ecp5: add synth_ecp5 -dff to work with -abc9Eddie Hung2020-05-142-12/+47
* ice40: synth_ice40 cleanupEddie Hung2020-05-141-13/+3
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