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Merge pull request #1603 from whitequark/ice40-ram_style
whitequark
2020-04-10
5
-2
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+137
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ecp5: do not map FFRAM if explicitly requested otherwise.
whitequark
2020-04-03
1
-1
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+3
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ice40: do not map FFRAM if explicitly requested otherwise.
whitequark
2020-04-03
1
-1
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+3
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ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
whitequark
2020-02-06
2
-0
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+71
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ice40: match memory inference attribute values case insensitive.
whitequark
2020-02-06
1
-0
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+1
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ice40: add support for both 1364.1 and LSE RAM/ROM attributes.
whitequark
2020-02-06
1
-0
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+59
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Merge pull request #1648 from YosysHQ/eddie/cmp2lcu
Eddie Hung
2020-04-03
5
-13
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+121
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cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmp
Eddie Hung
2020-04-03
1
-1
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+1
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cmp2lcu: fail if `LUT_WIDTH < 2
Eddie Hung
2020-04-03
1
-1
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+1
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synth: only techmap cmp2{lut,lcu} if -lut
Eddie Hung
2020-04-03
1
-1
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+1
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synth: use +/cmp2lcu.v in generic 'synth' too
Eddie Hung
2020-04-03
1
-2
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+2
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Cleanup +/cmp2lut.v
Eddie Hung
2020-04-03
1
-8
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+0
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synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'
Eddie Hung
2020-04-03
1
-2
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+1
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+/cmp2lcu.v to work efficiently for fully/partially constant inputs
Eddie Hung
2020-04-03
1
-33
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+42
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Refactor +/cmp2lcu.v into recursive techmap
Eddie Hung
2020-04-03
1
-38
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+65
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Cleanup
Eddie Hung
2020-04-03
1
-31
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+28
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Cleanup cmp2lcu.v
Eddie Hung
2020-04-03
1
-16
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+16
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techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu
Eddie Hung
2020-04-03
2
-0
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+84
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cmp2lut: comment out unused since 362f4f9
Eddie Hung
2020-04-03
1
-8
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+8
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Merge pull request #1767 from YosysHQ/eddie/idstrings
Eddie Hung
2020-04-02
16
-387
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+387
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kernel: big fat patch to use more ID::*, otherwise ID(*)
Eddie Hung
2020-04-02
16
-366
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+366
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kernel: use more ID::*
Eddie Hung
2020-04-02
5
-26
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+26
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simcells.v: Generate the fine FF cell types by a python script.
Marcin KoĆcielnicki
2020-04-02
2
-19
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+270
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Fix indentation in `techlibs/ice40/synth_ice40.cc`.
Alberto Gonzalez
2020-04-01
1
-4
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+4
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Merge pull request #1794 from YosysHQ/dave/mince-abc9-fix
David Shah
2020-03-21
1
-0
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+1
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ice40: Map unmapped 'mince' DFFs to gate level
David Shah
2020-03-20
1
-0
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+1
*
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ice40: Fix typos in SPRAM ABC9 timing specs
Sylvain Munaut
2020-03-20
1
-2
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+2
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xilinx: Mark IOBUFDS.IOB as external pad
Marcin KoĆcielnicki
2020-03-20
2
-1
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+2
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ice40: Fix SPRAM model to keep data stable if chipselect is low
Sylvain Munaut
2020-03-14
1
-5
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+8
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Fix invalid verilog syntax
Miodrag Milanovic
2020-03-14
1
-1
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+1
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Merge pull request #1716 from zeldin/ecp5_fix
N. Engelhardt
2020-03-09
1
-2
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+0
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remove unused parameters
N. Engelhardt
2020-03-06
1
-3
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+0
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ecp5: Add missing parameter to \$__ECP5_PDPW16KD
Marcus Comstedt
2020-02-22
1
-0
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+1
*
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ice40: fix specify for ICE40_{LP,U}
Eddie Hung
2020-03-05
1
-4
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+4
*
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ice40: fix implicit signal in specify, also clamp negative times to 0
Eddie Hung
2020-03-04
1
-22
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+22
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Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1
Eddie Hung
2020-03-04
4
-109
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+244
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xilinx: consider DSP48E1.ADREG
Eddie Hung
2020-03-04
4
-5
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+8
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xilinx: cleanup DSP48E1 handling for abc9
Eddie Hung
2020-03-04
3
-86
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+125
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xilinx: improve specify for DSP48E1
Eddie Hung
2020-03-04
1
-32
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+116
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xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v
Eddie Hung
2020-03-04
2
-5
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+14
*
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Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc
N. Engelhardt
2020-03-03
2
-6
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+39
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Add -flowmap to synth and synth_ice40
Dan Ravensloft
2020-02-28
2
-6
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+39
*
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Merge pull request #1724 from YosysHQ/eddie/abc9_specify
Eddie Hung
2020-03-02
30
-1440
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+2803
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Remove RAMB{18,36}E1 from cells_xtra.py
Eddie Hung
2020-02-27
1
-2
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+2
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xilinx: Update RAMB* specify entries
Eddie Hung
2020-02-27
1
-11
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+42
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ice40: add delays to SB_CARRY
Eddie Hung
2020-02-27
1
-0
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+30
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xilinx: add delays to INV
Eddie Hung
2020-02-27
1
-0
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+3
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More +/ice40/cells_sim.v fixes
Eddie Hung
2020-02-27
1
-27
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+27
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Make +/xilinx/cells_sim.v legal
Eddie Hung
2020-02-27
1
-76
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+78
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Get rid of (* abc9_{arrival,required} *) entirely
Eddie Hung
2020-02-27
3
-530
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+496
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