aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx
Commit message (Expand)AuthorAgeFilesLines
* Fix box nameEddie Hung2019-09-271-1/+1
* Missing an '&'Eddie Hung2019-09-261-1/+1
* Use extractinv for synth_xilinx -iseMarcin Kościelnicki2019-09-198-90/+502
* xilinx: Make blackbox library family-dependent.Marcin Kościelnicki2019-09-157-1024/+19252
* synth_xilinx: Support init values on Spartan 6 flip-flops properly.Marcin Kościelnicki2019-09-075-53/+219
* Resolve TODO with pin assignments for SRL*Eddie Hung2019-09-041-4/+2
* Add commentsEddie Hung2019-09-021-1/+9
* Remove trailing spaceEddie Hung2019-08-301-2/+2
* Merge branch 'eddie/xilinx_srl' into xaig_arrivalEddie Hung2019-08-281-15/+22
|\
| * Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-287-194/+623
| |\
| * \ Merge branch 'master' into eddie/xilinx_srlEddie Hung2019-08-261-0/+8
| |\ \
| * | | xilinx_srl now copes with word-level flops $dff{,e}Eddie Hung2019-08-231-8/+3
| * | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-231-8/+16
| |\ \ \
| * | | | Add variable length support to xilinx_srlEddie Hung2019-08-211-4/+3
| * | | | abc9 to perform new 'map_ffs' before 'map_luts'Eddie Hung2019-08-211-3/+18
| * | | | Add init supportEddie Hung2019-08-211-1/+1
* | | | | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-287-195/+653
|\ \ \ \ \
| * | | | | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendorEddie Hung2019-08-281-3/+8
| | |_|_|/ | |/| | |
| * | | | xilinx: Add SRLC16E primitive.Marcin Kościelnicki2019-08-271-1/+21
| * | | | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-261-0/+8
| |\ \ \ \ | | | |_|/ | | |/| |
| | * | | Add undocumented featureEddie Hung2019-08-231-0/+8
| | | |/ | | |/|
| * | | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-1/+1
| |\| |
| * | | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-11/+22
| |\ \ \
| * \ \ \ Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-235-30/+39
| |\ \ \ \ | | | |_|/ | | |/| |
| * | | | move attributes to wiresMarcin Kościelnicki2019-08-136-283/+537
| * | | | minor review fixesMarcin Kościelnicki2019-08-131-1/+1
| * | | | review fixesMarcin Kościelnicki2019-08-131-18/+27
| * | | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-136-71/+220
* | | | | Put attributes above portEddie Hung2019-08-232-27/+62
* | | | | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-231-5/+10
|\ \ \ \ \ | | |_|_|/ | |/| | |
| * | | | Forgot oneEddie Hung2019-08-231-1/+2
| | |_|/ | |/| |
| * | | Put abc_* attributes above portEddie Hung2019-08-231-7/+14
| | |/ | |/|
* | | Use semicolonEddie Hung2019-08-211-1/+1
* | | techmap before readEddie Hung2019-08-211-1/+1
* | | Add abc_arrival to SRL*Eddie Hung2019-08-211-3/+5
* | | OopsEddie Hung2019-08-201-1/+1
* | | xilinx to use abc_map.v with -max_iter 1Eddie Hung2019-08-206-171/+26
* | | Add reference to FD* timingEddie Hung2019-08-201-0/+2
* | | Remove sequential extensionEddie Hung2019-08-206-359/+17
* | | Remove SRL* delays from cells_sim.vEddie Hung2019-08-201-5/+3
* | | LUTMUX -> LUTMUX6Eddie Hung2019-08-201-2/+2
* | | Cleanup techmap in map_lutsEddie Hung2019-08-201-3/+5
* | | Move `techmap abc_map.v` into map_lutsEddie Hung2019-08-201-1/+2
* | | Remove delays from abc_map.vEddie Hung2019-08-201-5/+2
* | | TypoEddie Hung2019-08-201-1/+1
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-204-16/+19
|\| |
| * | Merge pull request #1209 from YosysHQ/eddie/synth_xilinxEddie Hung2019-08-204-16/+19
| |\ \
| | * | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinxEddie Hung2019-08-203-6/+6
| | |\|
| | * | Update Makefile tooEddie Hung2019-07-181-2/+2
| | * | Work in progress for renaming labels/options in synth_xilinxEddie Hung2019-07-183-14/+17