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xilinx
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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
Eddie Hung
2019-08-30
1
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+8
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Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
Eddie Hung
2019-08-28
1
-3
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+8
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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
Eddie Hung
2019-08-28
7
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+623
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xilinx: Add SRLC16E primitive.
Marcin Kościelnicki
2019-08-27
1
-1
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+21
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Merge branch 'master' into mwk/xilinx_bufgmap
Eddie Hung
2019-08-26
1
-0
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+8
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Merge branch 'master' into mwk/xilinx_bufgmap
Eddie Hung
2019-08-23
1
-1
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+1
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Merge branch 'master' into mwk/xilinx_bufgmap
Eddie Hung
2019-08-23
1
-11
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+22
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Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
Eddie Hung
2019-08-23
5
-30
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+39
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move attributes to wires
Marcin Kościelnicki
2019-08-13
6
-283
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+537
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minor review fixes
Marcin Kościelnicki
2019-08-13
1
-1
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+1
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review fixes
Marcin Kościelnicki
2019-08-13
1
-18
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+27
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Add clock buffer insertion pass, improve iopadmap.
Marcin Kościelnicki
2019-08-13
6
-71
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+220
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Merge branch 'master' into eddie/xilinx_srl
Eddie Hung
2019-08-26
1
-0
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+8
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Add undocumented feature
Eddie Hung
2019-08-23
1
-0
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+8
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xilinx_srl now copes with word-level flops $dff{,e}
Eddie Hung
2019-08-23
1
-8
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+3
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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
Eddie Hung
2019-08-23
1
-8
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+16
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Forgot one
Eddie Hung
2019-08-23
1
-1
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+2
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Put abc_* attributes above port
Eddie Hung
2019-08-23
1
-7
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+14
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Add variable length support to xilinx_srl
Eddie Hung
2019-08-21
1
-4
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+3
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abc9 to perform new 'map_ffs' before 'map_luts'
Eddie Hung
2019-08-21
1
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+18
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Add init support
Eddie Hung
2019-08-21
1
-1
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+1
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Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
Eddie Hung
2019-08-20
4
-16
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+19
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Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
Eddie Hung
2019-08-20
3
-6
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+6
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Update Makefile too
Eddie Hung
2019-07-18
1
-2
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+2
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Work in progress for renaming labels/options in synth_xilinx
Eddie Hung
2019-07-18
3
-14
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+17
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Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
Eddie Hung
2019-08-19
1
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+2
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Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules
Eddie Hung
2019-08-16
1
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+20
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stoi -> atoi
Eddie Hung
2019-08-07
1
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+1
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RST -> RSTBRST for RAMB8BWER
Eddie Hung
2019-07-29
1
-3
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+3
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xilinx: Fix missing cell name underscore in cells_map.v
David Shah
2019-07-25
1
-2
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+2
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Merge pull request #1182 from koriakin/xc6s-bram
Eddie Hung
2019-07-11
9
-8
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+598
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synth_xilinx: Initial Spartan 6 block RAM inference support.
Marcin Kościelnicki
2019-07-11
9
-8
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+598
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xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Viv...
Marcin Kościelnicki
2019-07-11
2
-6
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+6
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Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime
Eddie Hung
2019-07-10
1
-5
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+8
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Error out if -abc9 and -retime specified
Eddie Hung
2019-07-10
1
-5
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+8
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Add some spacing
Eddie Hung
2019-07-10
1
-9
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+9
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Add some ASCII art explaining mux decomposition
Eddie Hung
2019-07-10
1
-0
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+21
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Call muxpack and pmux2shiftx before cmp2lut
Eddie Hung
2019-07-09
1
-9
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+12
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Restore opt_clean back to original place
Eddie Hung
2019-07-09
1
-2
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+1
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Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
Eddie Hung
2019-07-09
1
-0
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+2
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Extend using A[1] to preserve don't care
Eddie Hung
2019-07-09
1
-1
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+9
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Extend during mux decomposition with 1'bx
Eddie Hung
2019-07-09
1
-24
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+3
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Fix typo and comments
Eddie Hung
2019-07-09
1
-4
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+4
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-07-09
1
-19
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+25
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Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup
Eddie Hung
2019-07-02
1
-0
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+2
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Cleanup SRL inference/make more consistent
Eddie Hung
2019-06-29
1
-19
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+25
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synth_xilinx to call commands of synth -coarse directly
Eddie Hung
2019-07-09
1
-3
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+20
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Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""
Eddie Hung
2019-07-09
1
-2
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+2
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Fix spacing
Eddie Hung
2019-07-09
1
-1
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+1
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Fix spacing
Eddie Hung
2019-07-09
1
-1
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+1
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