index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
techlibs
/
xilinx
Commit message (
Expand
)
Author
Age
Files
Lines
*
synth_xilinx -arch -> -family, consistent with older synth_intel
Eddie Hung
2019-06-27
1
-7
/
+8
*
Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymux
Eddie Hung
2019-06-27
1
-6
/
+28
|
\
|
*
Grrr
Eddie Hung
2019-06-26
1
-2
/
+2
|
*
Fix spacing
Eddie Hung
2019-06-26
1
-5
/
+5
|
*
Oops. Actually use nocarry flag as spotted by @koriakin
Eddie Hung
2019-06-26
1
-5
/
+7
|
*
Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriak...
Eddie Hung
2019-06-26
1
-4
/
+24
|
|
\
|
|
*
synth_xilinx: Add -nocarry and -nomux options.
Marcin KoĆcielnicki
2019-04-30
1
-7
/
+26
*
|
|
Simulation model verilog fix
Miodrag Milanovic
2019-06-26
1
-1
/
+1
|
/
/
*
|
Add RAM32X1D support
Eddie Hung
2019-06-24
5
-20
/
+73
*
|
Remove extra newline
Eddie Hung
2019-06-03
1
-1
/
+0
*
|
Execute techmap and arith_map simultaneously
Eddie Hung
2019-06-03
1
-6
/
+6
*
|
Add "min bits" and "min wports" to xilinx dram rules
Eddie Hung
2019-05-23
1
-0
/
+4
*
|
Add "stat -tech xilinx"
Clifford Wolf
2019-05-11
1
-1
/
+1
*
|
Add "synth_xilinx -arch"
Clifford Wolf
2019-05-07
1
-1
/
+13
*
|
Rename cells_map.v to prevent clash with ff_map.v
Eddie Hung
2019-05-03
1
-6
/
+8
*
|
Back to passing all xc7srl tests!
Eddie Hung
2019-05-01
1
-5
/
+4
*
|
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
Eddie Hung
2019-05-01
1
-165
/
+97
|
\
\
|
*
|
Refactor synth_xilinx to auto-generate doc
Eddie Hung
2019-04-26
1
-153
/
+95
*
|
|
WIP
Eddie Hung
2019-04-28
1
-36
/
+22
*
|
|
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
Eddie Hung
2019-04-28
2
-9
/
+12
*
|
|
Revert synth_xilinx 'fine' label more to how it used to be...
Eddie Hung
2019-04-26
1
-21
/
+40
|
|
/
|
/
|
*
|
Where did this check come from!?!
Eddie Hung
2019-04-26
1
-1
/
+0
|
/
*
Update help message
Eddie Hung
2019-04-22
1
-1
/
+1
*
Move 'shregmap -tech xilinx' into map_cells
Eddie Hung
2019-04-22
1
-17
/
+20
*
Merge remote-tracking branch 'origin/master' into xc7srl
Eddie Hung
2019-04-22
1
-0
/
+2
|
\
|
*
Re-added clean after techmap in synth_xilinx
Clifford Wolf
2019-04-22
1
-0
/
+2
*
|
Tidy up, fix for -nosrl
Eddie Hung
2019-04-21
2
-12
/
+16
*
|
Merge branch 'map_cells_before_map_luts' into xc7srl
Eddie Hung
2019-04-21
1
-2
/
+2
|
\
|
|
*
Merge branch 'master' into map_cells_before_map_luts
Eddie Hung
2019-04-21
5
-56
/
+76
|
|
\
*
|
|
Add comments
Eddie Hung
2019-04-21
1
-0
/
+7
*
|
|
Use new pmux2shiftx from #944, remove my old attempt
Eddie Hung
2019-04-21
1
-3
/
+8
*
|
|
Merge remote-tracking branch 'origin' into xc7srl
Eddie Hung
2019-04-20
3
-41
/
+60
|
\
\
\
|
|
|
/
|
|
/
|
|
*
|
Revert "synth_* with -retime option now calls abc with -D 1 as well"
Eddie Hung
2019-04-18
1
-2
/
+2
|
*
|
Merge branch 'master' into eddie/fix_retime
Eddie Hung
2019-04-18
3
-41
/
+60
|
|
\
\
|
|
*
|
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Keith Rothman
2019-04-12
3
-52
/
+14
|
|
*
|
Fix LUT6_2 definition.
Keith Rothman
2019-04-09
1
-3
/
+3
|
|
*
|
Add additional cells sim models for core 7-series primatives.
Keith Rothman
2019-04-09
1
-0
/
+57
|
*
|
|
synth_* with -retime option now calls abc with -D 1 as well
Eddie Hung
2019-04-10
1
-2
/
+2
*
|
|
|
Call shregmap twice -- once for variable, another for fixed
Eddie Hung
2019-04-05
2
-8
/
+14
*
|
|
|
Move dffinit til after abc
Eddie Hung
2019-04-05
3
-2
/
+2
*
|
|
|
Merge branch 'eddie/fix_retime' into xc7srl
Eddie Hung
2019-04-05
4
-11
/
+12
|
\
|
|
|
|
*
|
|
Move techamp t:$_DFF_?N? to before abc call
Eddie Hung
2019-04-05
1
-2
/
+2
|
*
|
|
Retry
Eddie Hung
2019-04-05
1
-1
/
+1
|
*
|
|
Resolve @daveshah1 comment, update synth_xilinx help
Eddie Hung
2019-04-05
2
-7
/
+9
|
*
|
|
synth_xilinx to techmap FFs after abc call, otherwise -retime fails
Eddie Hung
2019-04-05
1
-3
/
+3
|
|
/
/
*
|
|
techmap inside map_cells stage
Eddie Hung
2019-04-05
2
-2
/
+1
*
|
|
Merge branch 'map_cells_before_map_luts' into xc7srl
Eddie Hung
2019-04-04
1
-0
/
+1
|
\
\
\
|
|
|
/
|
|
/
|
|
*
|
Missing techmap entry in help
Eddie Hung
2019-04-04
1
-0
/
+1
*
|
|
Use soft-logic, not LUT3 instantiation
Eddie Hung
2019-04-04
1
-4
/
+2
*
|
|
Merge branch 'map_cells_before_map_luts' into xc7srl
Eddie Hung
2019-04-04
1
-12
/
+12
|
\
|
|
[next]