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* synth_xilinx -arch -> -family, consistent with older synth_intelEddie Hung2019-06-271-7/+8
* Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymuxEddie Hung2019-06-271-6/+28
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| * GrrrEddie Hung2019-06-261-2/+2
| * Fix spacingEddie Hung2019-06-261-5/+5
| * Oops. Actually use nocarry flag as spotted by @koriakinEddie Hung2019-06-261-5/+7
| * Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriak...Eddie Hung2019-06-261-4/+24
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| | * synth_xilinx: Add -nocarry and -nomux options.Marcin Kościelnicki2019-04-301-7/+26
* | | Simulation model verilog fixMiodrag Milanovic2019-06-261-1/+1
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* | Add RAM32X1D supportEddie Hung2019-06-245-20/+73
* | Remove extra newlineEddie Hung2019-06-031-1/+0
* | Execute techmap and arith_map simultaneouslyEddie Hung2019-06-031-6/+6
* | Add "min bits" and "min wports" to xilinx dram rulesEddie Hung2019-05-231-0/+4
* | Add "stat -tech xilinx"Clifford Wolf2019-05-111-1/+1
* | Add "synth_xilinx -arch"Clifford Wolf2019-05-071-1/+13
* | Rename cells_map.v to prevent clash with ff_map.vEddie Hung2019-05-031-6/+8
* | Back to passing all xc7srl tests!Eddie Hung2019-05-011-5/+4
* | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fineEddie Hung2019-05-011-165/+97
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| * | Refactor synth_xilinx to auto-generate docEddie Hung2019-04-261-153/+95
* | | WIPEddie Hung2019-04-281-36/+22
* | | Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-04-282-9/+12
* | | Revert synth_xilinx 'fine' label more to how it used to be...Eddie Hung2019-04-261-21/+40
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* | Where did this check come from!?!Eddie Hung2019-04-261-1/+0
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* Update help messageEddie Hung2019-04-221-1/+1
* Move 'shregmap -tech xilinx' into map_cellsEddie Hung2019-04-221-17/+20
* Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-04-221-0/+2
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| * Re-added clean after techmap in synth_xilinxClifford Wolf2019-04-221-0/+2
* | Tidy up, fix for -nosrlEddie Hung2019-04-212-12/+16
* | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-211-2/+2
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| * Merge branch 'master' into map_cells_before_map_lutsEddie Hung2019-04-215-56/+76
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* | | Add commentsEddie Hung2019-04-211-0/+7
* | | Use new pmux2shiftx from #944, remove my old attemptEddie Hung2019-04-211-3/+8
* | | Merge remote-tracking branch 'origin' into xc7srlEddie Hung2019-04-203-41/+60
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| * | Revert "synth_* with -retime option now calls abc with -D 1 as well"Eddie Hung2019-04-181-2/+2
| * | Merge branch 'master' into eddie/fix_retimeEddie Hung2019-04-183-41/+60
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| | * | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
| | * | Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
| | * | Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
| * | | synth_* with -retime option now calls abc with -D 1 as wellEddie Hung2019-04-101-2/+2
* | | | Call shregmap twice -- once for variable, another for fixedEddie Hung2019-04-052-8/+14
* | | | Move dffinit til after abcEddie Hung2019-04-053-2/+2
* | | | Merge branch 'eddie/fix_retime' into xc7srlEddie Hung2019-04-054-11/+12
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| * | | Move techamp t:$_DFF_?N? to before abc callEddie Hung2019-04-051-2/+2
| * | | RetryEddie Hung2019-04-051-1/+1
| * | | Resolve @daveshah1 comment, update synth_xilinx helpEddie Hung2019-04-052-7/+9
| * | | synth_xilinx to techmap FFs after abc call, otherwise -retime failsEddie Hung2019-04-051-3/+3
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* | | techmap inside map_cells stageEddie Hung2019-04-052-2/+1
* | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-0/+1
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| * | Missing techmap entry in helpEddie Hung2019-04-041-0/+1
* | | Use soft-logic, not LUT3 instantiationEddie Hung2019-04-041-4/+2
* | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-12/+12
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