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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-04 08:13:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-04 08:13:10 -0700 |
| commit | e3f20b17afce26f08b277b757e32c33a473a8571 (patch) | |
| tree | 97228c2a17f2d9a7a34f3168545d1e5bed3b93f9 /techlibs/xilinx | |
| parent | d9cb787391143a1749954f9e442fd37a13668b08 (diff) | |
| download | yosys-e3f20b17afce26f08b277b757e32c33a473a8571.tar.gz yosys-e3f20b17afce26f08b277b757e32c33a473a8571.tar.bz2 yosys-e3f20b17afce26f08b277b757e32c33a473a8571.zip | |
Missing techmap entry in help
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 1260ab106..b82ab9337 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -123,6 +123,7 @@ struct SynthXilinxPass : public Pass log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n"); log(" abc -lut 5 [-dff] (with '-vpr' only!)\n"); log(" clean\n"); + log(" techmap -map +/xilinx/lut_map.v\n"); log("\n"); log(" check:\n"); log(" hierarchy -check\n"); |