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author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 15:31:54 -0700 |
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committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 15:31:54 -0700 |
commit | 23a6533e98df384afdeb38891404da17533c836b (patch) | |
tree | c7c6ce5abc1b126e6ce111c29b3c7cc8e0d60462 /techlibs/xilinx | |
parent | 3c253818cab2013dc4db55732d3e21cfa0dc3f19 (diff) | |
download | yosys-23a6533e98df384afdeb38891404da17533c836b.tar.gz yosys-23a6533e98df384afdeb38891404da17533c836b.tar.bz2 yosys-23a6533e98df384afdeb38891404da17533c836b.zip |
Retry
Diffstat (limited to 'techlibs/xilinx')
-rw-r--r-- | techlibs/xilinx/ff_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v index c323206e8..3d5f78770 100644 --- a/techlibs/xilinx/ff_map.v +++ b/techlibs/xilinx/ff_map.v @@ -30,7 +30,7 @@ module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPL module \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule module \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PN0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +module \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule module \$_DFF_PP0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule module \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule |