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path: root/techlibs/xilinx/xc7_xcu_brams.txt
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* xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.Marcin Koƛcielnicki2020-02-071-0/+2
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* Add unconditional match blocks for force RAMEddie Hung2019-12-161-4/+36
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* Update xc7/xcu bram rulesEddie Hung2019-12-161-8/+4
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* Removing fixed attribute value to !ramstyle rulesDiego H2019-12-151-4/+4
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* Merging attribute rules into a single match block; Adding testsDiego H2019-12-151-18/+12
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* Refactoring memory attribute matching based on IEEE 1364.1 and Tool specificDiego H2019-12-131-0/+19
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* Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.Diego H2019-12-121-5/+5
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* Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1Diego H2019-12-121-2/+2
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* Adjusting Vivado's BRAM min bits threshold for RAMB18E1Diego H2019-11-271-2/+5
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* xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-231-0/+105
Signed-off-by: David Shah <dave@ds0.me>