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authorDavid Shah <dave@ds0.me>2019-10-18 13:24:19 +0100
committerDavid Shah <dave@ds0.me>2019-10-23 11:47:37 +0100
commit6769d31ddbab341940af9b42b538fca60797fdf4 (patch)
treea80cd15e8fdd3d4cf58ea30a7596c5d6a2a8b64b /techlibs/xilinx/xc7_xcu_brams.txt
parentf02623abb5d8338f034d7069844418af8912ab0f (diff)
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xilinx: Add support for UltraScale[+] BRAM mapping
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/xilinx/xc7_xcu_brams.txt')
-rw-r--r--techlibs/xilinx/xc7_xcu_brams.txt105
1 files changed, 105 insertions, 0 deletions
diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt
new file mode 100644
index 000000000..f1161114e
--- /dev/null
+++ b/techlibs/xilinx/xc7_xcu_brams.txt
@@ -0,0 +1,105 @@
+
+bram $__XILINX_RAMB36_SDP
+ init 1
+ abits 9
+ dbits 72
+ groups 2
+ ports 1 1
+ wrmode 0 1
+ enable 1 8
+ transp 0 0
+ clocks 2 3
+ clkpol 2 3
+endbram
+
+bram $__XILINX_RAMB18_SDP
+ init 1
+ abits 9
+ dbits 36
+ groups 2
+ ports 1 1
+ wrmode 0 1
+ enable 1 4
+ transp 0 0
+ clocks 2 3
+ clkpol 2 3
+endbram
+
+bram $__XILINX_RAMB36_TDP
+ init 1
+ abits 10 @a10d36
+ dbits 36 @a10d36
+ abits 11 @a11d18
+ dbits 18 @a11d18
+ abits 12 @a12d9
+ dbits 9 @a12d9
+ abits 13 @a13d4
+ dbits 4 @a13d4
+ abits 14 @a14d2
+ dbits 2 @a14d2
+ abits 15 @a15d1
+ dbits 1 @a15d1
+ groups 2
+ ports 1 1
+ wrmode 0 1
+ enable 1 4 @a10d36
+ enable 1 2 @a11d18
+ enable 1 1 @a12d9 @a13d4 @a14d2 @a15d1
+ transp 0 0
+ clocks 2 3
+ clkpol 2 3
+endbram
+
+bram $__XILINX_RAMB18_TDP
+ init 1
+ abits 10 @a10d18
+ dbits 18 @a10d18
+ abits 11 @a11d9
+ dbits 9 @a11d9
+ abits 12 @a12d4
+ dbits 4 @a12d4
+ abits 13 @a13d2
+ dbits 2 @a13d2
+ abits 14 @a14d1
+ dbits 1 @a14d1
+ groups 2
+ ports 1 1
+ wrmode 0 1
+ enable 1 2 @a10d18
+ enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
+ transp 0 0
+ clocks 2 3
+ clkpol 2 3
+endbram
+
+match $__XILINX_RAMB36_SDP
+ min bits 4096
+ min efficiency 5
+ shuffle_enable B
+ make_transp
+ or_next_if_better
+endmatch
+
+match $__XILINX_RAMB18_SDP
+ min bits 4096
+ min efficiency 5
+ shuffle_enable B
+ make_transp
+ or_next_if_better
+endmatch
+
+match $__XILINX_RAMB36_TDP
+ min bits 4096
+ min efficiency 5
+ shuffle_enable B
+ make_transp
+ or_next_if_better
+endmatch
+
+match $__XILINX_RAMB18_TDP
+ min bits 4096
+ min efficiency 5
+ shuffle_enable B
+ make_transp
+endmatch
+